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arm: init CNTVOFF #2052

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merged 1 commit into from
Jan 17, 2018
Merged

arm: init CNTVOFF #2052

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6 changes: 6 additions & 0 deletions core/arch/arm/include/arm32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,12 @@
/* Valid if FSR.LPAE is 0 */
#define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1))

/* ID_PFR1 bit fields */
#define IDPFR1_VIRT_SHIFT 12
#define IDPFR1_VIRT_MASK (0xF << IDPFR1_VIRT_SHIFT)
#define IDPFR1_GENTIMER_SHIFT 16
#define IDPFR1_GENTIMER_MASK (0xF << IDPFR1_GENTIMER_SHIFT)

#ifndef ASM
static inline uint32_t read_mpidr(void)
{
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8 changes: 8 additions & 0 deletions core/arch/arm/include/arm32_macros.S
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Expand Up @@ -40,6 +40,10 @@
mrc p15, 0, \reg, c0, c0, 5
.endm

.macro read_idpfr1 reg
mrc p15, 0, \reg, c0, c1, 1
.endm

.macro read_sctlr reg
mrc p15, 0, \reg, c1, c0, 0
.endm
Expand Down Expand Up @@ -270,6 +274,10 @@
mrc p15, 0, \reg, c13, c0, 4
.endm

.macro write_cntvoff reg0, reg1
mcrr p15, 4, \reg0, \reg1, c14
.endm

.macro read_clidr reg
/* Cache Level ID Register */
mrc p15, 1, \reg, c0, c0, 1
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1 change: 1 addition & 0 deletions core/arch/arm/plat-imx/conf.mk
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Expand Up @@ -80,6 +80,7 @@ include core/arch/arm/cpu/cortex-a7.mk

$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
CFG_BOOT_SECONDARY_REQUEST ?= y
CFG_INIT_CNTVOFF ?= y
endif

ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
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32 changes: 32 additions & 0 deletions core/arch/arm/sm/sm_a32.S
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Expand Up @@ -335,6 +335,38 @@ UNWIND( .fnstart)
cps #CPSR_MODE_MON
/* Point just beyond sm_ctx.sec */
sub sp, r0, #(SM_CTX_SIZE - SM_CTX_NSEC)

#ifdef CFG_INIT_CNTVOFF
read_scr r0
orr r0, r0, #SCR_NS /* Set NS bit in SCR */
write_scr r0
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Need an ISB after setting (and clearing) SCR[NS]?

Also, maybe use a sequence where we switch in non secure only if CNTVOFF is accessed. Yet, this is not a big issue: we're booting, no perf penalty...

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ISB is needed. I'll add it.

isb

/*
* Accessing CNTVOFF:
* If the implementation includes the Virtualization Extensions
* this is a RW register, accessible from Hyp mode, and
* from Monitor mode when SCR.NS is set to 1.
* If the implementation includes the Security Extensions
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here replace Security Extensions with Generic Timers?

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This comments are directly from ARM architecture reference mannual. So keep Security extensions.

* but not the Virtualization Extensions, an MCRR or MRRC to
* the CNTVOFF encoding is UNPREDICTABLE if executed in Monitor
* mode, regardless of the value of SCR.NS.
*/
read_idpfr1 r2
mov r3, r2
ands r3, r3, #IDPFR1_GENTIMER_MASK
beq .no_gentimer
ands r2, r2, #IDPFR1_VIRT_MASK
beq .no_gentimer
mov r2, #0
write_cntvoff r2, r2

.no_gentimer:
bic r0, r0, #SCR_NS /* Clr NS bit in SCR */
write_scr r0
isb
#endif

msr cpsr, r1

#ifdef CFG_CORE_WORKAROUND_SPECTRE_BP
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