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BBB_cci_mpf
The semantics of CCI-P transactions are deliberately simple. Channel 0 (system memory read) and channel 1 (system memory write) are completely unordered. Unlike traditional CPU memory interfaces, CCI-P even offers no order guarantee for a pair of memory writes to the same address! This decision is dictated by the reality of spatial logic: any FPGA area devoted to guaranteeing memory order takes away area that could be made available to user logic. The platform bitstream (blue bitstream) satisfies only the memory requirements common to all applications. These primitive CCI-P semantics are sufficient for kernels that read state from one buffer, compute and then stream out the result to another buffer. In addition to lack of order, CCI-P addresses are all physical and memory is allocated at page granularity — a restriction that can make large buffer management or pointer sharing with a software process difficult.
Some AFUs may require more complex memory semantics. Applications may depend on ordered read responses or ordered writes to the same address. Other features, such as virtual addressing with large buffer support may also be required.
Even AFUs with complex memory dependencies will likely require only a subset of the available options. Just as CCI-P is designed to minimize FPGA area, an ideal AFU-specific memory interface will implement only the features required by a given AFU. This is the strategy employed by MPF.
MPF is a collection of shims that transform CCI-P. The shims both consume and produce CCI-P structures, transforming the semantics of the interface without significant changes to the interface structures themselves. MPF components include:
- VTP (Virtual to Physical): Read and write from virtual addresses
- ROB (Reorder Buffer): Return read responses in request order
- WRO (Write/Read Order): Enforce same-address write/read and write/write ordering
- VC Map: Often used in combination with WRO — a mechanism for avoiding inter-physical channel ordering problems that would normally require write fences
- PWRITE (Partial Write): Masked writes, implemented as read-modify-write
- MPF RTL interface
- Importing MPF for simulation or synthesis
- MPF software