Update layers (enable I2C4 interrupts)

Open-CMSIS-Pack · Sep 12, 2024 · ff632f7 · ff632f7
1 parent 18d3637
commit ff632f7
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Showing 11 changed files with 85 additions and 3 deletions.
diff --git a/.ci/Layers/Default_GCC/CubeMX/MX_Device/MX_Device.h b/.ci/Layers/Default_GCC/CubeMX/MX_Device/MX_Device.h
@@ -1,6 +1,6 @@
 /******************************************************************************
  * File Name   : MX_Device.h
- * Date        : 09/09/2024 10:19:22
+ * Date        : 12/09/2024 13:18:29
  * Description : STM32Cube MX parameter definitions
  * Note        : This file is generated with a generator out of the
  *               STM32CubeMX project and its generated files (DO NOT EDIT!)

diff --git a/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Inc/stm32h7xx_it.h b/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Inc/stm32h7xx_it.h
@@ -57,6 +57,8 @@ void USART3_IRQHandler(void);
 void ETH_IRQHandler(void);
 void OTG_HS_IRQHandler(void);
 void SPI5_IRQHandler(void);
+void I2C4_EV_IRQHandler(void);
+void I2C4_ER_IRQHandler(void);
 void TIM23_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 

diff --git a/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/STM32CubeMX.ioc b/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/STM32CubeMX.ioc
@@ -220,6 +220,8 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.ETH_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.I2C4_ER_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
+NVIC.I2C4_EV_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.OTG_HS_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true

diff --git a/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Src/stm32h7xx_hal_msp.c b/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Src/stm32h7xx_hal_msp.c
@@ -604,6 +604,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
 
     /* Peripheral clock enable */
     __HAL_RCC_I2C4_CLK_ENABLE();
+    /* I2C4 interrupt Init */
+    HAL_NVIC_SetPriority(I2C4_EV_IRQn, 8, 0);
+    HAL_NVIC_EnableIRQ(I2C4_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C4_ER_IRQn, 8, 0);
+    HAL_NVIC_EnableIRQ(I2C4_ER_IRQn);
   /* USER CODE BEGIN I2C4_MspInit 1 */
 
   /* USER CODE END I2C4_MspInit 1 */
@@ -636,6 +641,9 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
 
     HAL_GPIO_DeInit(I2C4_SCL_GPIO_Port, I2C4_SCL_Pin);
 
+    /* I2C4 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(I2C4_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C4_ER_IRQn);
   /* USER CODE BEGIN I2C4_MspDeInit 1 */
 
   /* USER CODE END I2C4_MspDeInit 1 */

diff --git a/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Src/stm32h7xx_it.c b/.ci/Layers/Default_GCC/CubeMX/STM32CubeMX/Src/stm32h7xx_it.c
@@ -56,6 +56,7 @@
 
 /* External variables --------------------------------------------------------*/
 extern ETH_HandleTypeDef heth;
+extern I2C_HandleTypeDef hi2c4;
 extern SPI_HandleTypeDef hspi5;
 extern UART_HandleTypeDef huart1;
 extern UART_HandleTypeDef huart3;
@@ -234,6 +235,34 @@ void SPI5_IRQHandler(void)
   /* USER CODE END SPI5_IRQn 1 */
 }
 
+/**
+  * @brief This function handles I2C4 event interrupt.
+  */
+void I2C4_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C4_EV_IRQn 0 */
+
+  /* USER CODE END I2C4_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c4);
+  /* USER CODE BEGIN I2C4_EV_IRQn 1 */
+
+  /* USER CODE END I2C4_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C4 error interrupt.
+  */
+void I2C4_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C4_ER_IRQn 0 */
+
+  /* USER CODE END I2C4_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c4);
+  /* USER CODE BEGIN I2C4_ER_IRQn 1 */
+
+  /* USER CODE END I2C4_ER_IRQn 1 */
+}
+
 /**
   * @brief This function handles TIM23 global interrupt.
   */

diff --git a/.ci/README.md b/.ci/README.md
@@ -1,5 +1,5 @@
 # Continuous  Integration (CI) Test for Board Support Pack (BSP)
-  
+
 Content of `.ci` Directory   | Description
 :----------------------------|:-----------------
 `./Layers/Default_GCC`       | Default Board layer for the GCC compiler.

diff --git a/Layers/Default/CubeMX/MX_Device/MX_Device.h b/Layers/Default/CubeMX/MX_Device/MX_Device.h
@@ -1,6 +1,6 @@
 /******************************************************************************
  * File Name   : MX_Device.h
- * Date        : 09/09/2024 10:10:51
+ * Date        : 12/09/2024 13:16:07
  * Description : STM32Cube MX parameter definitions
  * Note        : This file is generated with a generator out of the
  *               STM32CubeMX project and its generated files (DO NOT EDIT!)

diff --git a/Layers/Default/CubeMX/STM32CubeMX/Inc/stm32h7xx_it.h b/Layers/Default/CubeMX/STM32CubeMX/Inc/stm32h7xx_it.h
@@ -57,6 +57,8 @@ void USART3_IRQHandler(void);
 void ETH_IRQHandler(void);
 void OTG_HS_IRQHandler(void);
 void SPI5_IRQHandler(void);
+void I2C4_EV_IRQHandler(void);
+void I2C4_ER_IRQHandler(void);
 void TIM23_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 

diff --git a/Layers/Default/CubeMX/STM32CubeMX/STM32CubeMX.ioc b/Layers/Default/CubeMX/STM32CubeMX/STM32CubeMX.ioc
@@ -220,6 +220,8 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.ETH_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.I2C4_ER_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
+NVIC.I2C4_EV_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.OTG_HS_IRQn=true\:8\:0\:true\:false\:true\:true\:true\:true

diff --git a/Layers/Default/CubeMX/STM32CubeMX/Src/stm32h7xx_hal_msp.c b/Layers/Default/CubeMX/STM32CubeMX/Src/stm32h7xx_hal_msp.c
@@ -604,6 +604,11 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
 
     /* Peripheral clock enable */
     __HAL_RCC_I2C4_CLK_ENABLE();
+    /* I2C4 interrupt Init */
+    HAL_NVIC_SetPriority(I2C4_EV_IRQn, 8, 0);
+    HAL_NVIC_EnableIRQ(I2C4_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C4_ER_IRQn, 8, 0);
+    HAL_NVIC_EnableIRQ(I2C4_ER_IRQn);
   /* USER CODE BEGIN I2C4_MspInit 1 */
 
   /* USER CODE END I2C4_MspInit 1 */
@@ -636,6 +641,9 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
 
     HAL_GPIO_DeInit(I2C4_SCL_GPIO_Port, I2C4_SCL_Pin);
 
+    /* I2C4 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(I2C4_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C4_ER_IRQn);
   /* USER CODE BEGIN I2C4_MspDeInit 1 */
 
   /* USER CODE END I2C4_MspDeInit 1 */

diff --git a/Layers/Default/CubeMX/STM32CubeMX/Src/stm32h7xx_it.c b/Layers/Default/CubeMX/STM32CubeMX/Src/stm32h7xx_it.c
@@ -56,6 +56,7 @@
 
 /* External variables --------------------------------------------------------*/
 extern ETH_HandleTypeDef heth;
+extern I2C_HandleTypeDef hi2c4;
 extern SPI_HandleTypeDef hspi5;
 extern UART_HandleTypeDef huart1;
 extern UART_HandleTypeDef huart3;
@@ -234,6 +235,34 @@ void SPI5_IRQHandler(void)
   /* USER CODE END SPI5_IRQn 1 */
 }
 
+/**
+  * @brief This function handles I2C4 event interrupt.
+  */
+void I2C4_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C4_EV_IRQn 0 */
+
+  /* USER CODE END I2C4_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c4);
+  /* USER CODE BEGIN I2C4_EV_IRQn 1 */
+
+  /* USER CODE END I2C4_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C4 error interrupt.
+  */
+void I2C4_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C4_ER_IRQn 0 */
+
+  /* USER CODE END I2C4_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c4);
+  /* USER CODE BEGIN I2C4_ER_IRQn 1 */
+
+  /* USER CODE END I2C4_ER_IRQn 1 */
+}
+
 /**
   * @brief This function handles TIM23 global interrupt.
   */