Skip create port if the lane set isn't available in ASIC

Signed-off-by: Ze Gan <ganze718@gmail.com>
Pterosaur · Sep 23, 2021 · f521da3 · f521da3
1 parent 86b4ede
commit f521da3
Show file tree

Hide file tree

Showing 2 changed files with 18 additions and 0 deletions.
diff --git a/orchagent/portsorch.cpp b/orchagent/portsorch.cpp
@@ -468,6 +468,7 @@ PortsOrch::PortsOrch(DBConnector *db, DBConnector *stateDb, vector<table_name_wi
 
         SWSS_LOG_NOTICE("Get port with lanes pid:%" PRIx64 " lanes:%s", port_list[i], tmp_lane_str.c_str());
         m_portListLaneMap[tmp_lane_set] = port_list[i];
+        m_availablePortSet.insert(tmp_lane_set);
     }
 
     /* Get default 1Q bridge and default VLAN */
@@ -2737,6 +2738,20 @@ void PortsOrch::doPortTask(Consumer &consumer)
 
                 for (auto it = m_lanesAliasSpeedMap.begin(); it != m_lanesAliasSpeedMap.end();)
                 {
+                    if (m_availablePortSet.find(it->first) == m_availablePortSet.end())
+                    {
+                        string tmp_lane_str = "";
+                        for (auto s : it->first)
+                        {
+                            tmp_lane_str += to_string(s) + " ";
+                        }
+                        tmp_lane_str = tmp_lane_str.substr(0, tmp_lane_str.size() - 1);
+
+                        SWSS_LOG_WARN("The lane set %s isn't available in ASIC", tmp_lane_str.c_str());
+                        it++;
+                        continue;
+                    }
+
                     if (m_portListLaneMap.find(it->first) == m_portListLaneMap.end())
                     {
                         if (!addPort(it->first, get<1>(it->second), get<2>(it->second), get<3>(it->second)))

diff --git a/orchagent/portsorch.h b/orchagent/portsorch.h
@@ -213,8 +213,11 @@ class PortsOrch : public Orch, public Subject
 
     port_config_state_t m_portConfigState = PORT_CONFIG_MISSING;
     sai_uint32_t m_portCount;
+    // m_portListLaneMap is the current enabled port list
     map<set<int>, sai_object_id_t> m_portListLaneMap;
     map<set<int>, tuple<string, uint32_t, int, string, int, string>> m_lanesAliasSpeedMap;
+    // m_availablePortSet is the available port list read from ASIC by SAI
+    set<set<int>> m_availablePortSet;
     map<string, Port> m_portList;
     unordered_map<sai_object_id_t, int> m_portOidToIndex;
     map<string, uint32_t> m_port_ref_count;