Merge branch 'rc-1.7.0'

examples/simulation_verilator/test_simulation_verilator.py

@@ -22,7 +22,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -41,7 +41,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -57,7 +57,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -76,7 +76,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -550,7 +550,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -569,7 +569,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,

examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py

@@ -17,7 +17,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -36,7 +36,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -138,7 +138,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -157,7 +157,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1127,7 +1127,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1146,7 +1146,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

@@ -16,7 +16,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -136,7 +136,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -155,7 +155,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1124,7 +1124,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1143,7 +1143,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -17,7 +17,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -36,7 +36,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -138,7 +138,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -157,7 +157,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1127,7 +1127,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1146,7 +1146,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

tests/extension/stream_/cast/test_stream_cast.py

@@ -128,13 +128,19 @@
   output signed [32-1:0] zdata
 );
 
+  wire signed [32-1:0] _cast_src_2;
+  assign _cast_src_2 = xdata;
   wire signed [64-1:0] _cast_data_2;
-  assign _cast_data_2 = xdata << 8;
+  assign _cast_data_2 = _cast_src_2 << 8;
+  wire signed [32-1:0] _cast_src_3;
+  assign _cast_src_3 = ydata;
   wire signed [64-1:0] _cast_data_3;
-  assign _cast_data_3 = ydata << 8;
+  assign _cast_data_3 = _cast_src_3 << 8;
   reg signed [64-1:0] _plus_data_4;
+  wire signed [64-1:0] _cast_src_5;
+  assign _cast_src_5 = _plus_data_4;
   wire signed [32-1:0] _cast_data_5;
-  assign _cast_data_5 = _plus_data_4 >>> 8;
+  assign _cast_data_5 = _cast_src_5 >>> 8;
   assign zdata = _cast_data_5;
 
   always @(posedge CLK) begin

tests/extension/thread_/stream_cast/thread_stream_cast.py

@@ -27,8 +27,8 @@ def mkLed():
     strm = vthread.Stream(m, 'mystream', clk, rst)
     a = strm.source('a')
     b = strm.source('b')
-    a = strm.Cast(a, 64, 0)
-    b = strm.Cast(b, 64, 0)
+    a = strm.Cast(a, 64, 4)
+    b = strm.Cast(b, 64, 4)
     c = a * b
     c = strm.Cast(c, 32, 0)
     strm.sink(c, 'c')

tests/extension/thread_/stream_fixed/thread_stream_fixed.py

@@ -39,7 +39,7 @@ def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
         strm.set_source('b', ram_b, offset, size)
         strm.set_sink('c', ram_c, offset, size)
-        const = vthread.fixed.FixedConst(3.5, point=point)
+        const = vthread.fixed.FixedConst(1, point=point)
         strm.set_constant('const', const)
         strm.run()
         strm.join()
@@ -48,10 +48,10 @@ def comp_sequential(size, offset):
         for i in range(size):
             a = ram_a.read(i + offset)
             b = ram_b.read(i + offset)
-            const = vthread.fixed.FixedConst(3.5, point=point)
+            const = vthread.fixed.FixedConst(1, point=point)
             c = a * b + const
             ram_c.write(i + offset, c)
-            print('a = %f, b = %f, const = %f, c =  %f' % (a, b, const, c))
+            print('a = %10g, b = %10g, const = %10g, c =  %10g' % (a, b, const, c))
 
     def check(size, offset_stream, offset_seq):
         all_ok = True

tests/extension/thread_/stream_fixed_different_point/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_fixed_different_point/test_thread_stream_fixed_different_point.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_fixed_different_point
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_fixed_different_point.run(filename=None, simtype=simtype,
+                                                   outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')