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Merge branch 'rc-1.5.2'
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@shtaxxx
shtaxxx committed Nov 29, 2018
2 parents ee30238 + f7d46ee commit 536d48d
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Showing 11 changed files with 96 additions and 96 deletions.
48 changes: 24 additions & 24 deletions examples/thread_add_ipcore/test_thread_add_ipcore.py
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Original file line number Diff line number Diff line change
Expand Up @@ -807,98 +807,98 @@
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
_saxi_register_7 <= saxi_wdata;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 0)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 1) begin
_saxi_register_0 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 1)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_1 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 2)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_2 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 3)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_3 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 4)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_4 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 5)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_5 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 6)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_6 <= 0;
end
if((_saxi_register_0 == 1) && (th_add == 2) && (0 == 7)) begin
if((_saxi_register_0 == 1) && (th_add == 2) && 0) begin
_saxi_register_7 <= 0;
end
if((th_add == 6) && (4 == 0)) begin
if((th_add == 6) && 0) begin
_saxi_register_0 <= _th_add_c_2;
_saxi_flag_0 <= 0;
end
if((th_add == 6) && (4 == 1)) begin
if((th_add == 6) && 0) begin
_saxi_register_1 <= _th_add_c_2;
_saxi_flag_1 <= 0;
end
if((th_add == 6) && (4 == 2)) begin
if((th_add == 6) && 0) begin
_saxi_register_2 <= _th_add_c_2;
_saxi_flag_2 <= 0;
end
if((th_add == 6) && (4 == 3)) begin
if((th_add == 6) && 0) begin
_saxi_register_3 <= _th_add_c_2;
_saxi_flag_3 <= 0;
end
if((th_add == 6) && (4 == 4)) begin
if((th_add == 6) && 1) begin
_saxi_register_4 <= _th_add_c_2;
_saxi_flag_4 <= 0;
end
if((th_add == 6) && (4 == 5)) begin
if((th_add == 6) && 0) begin
_saxi_register_5 <= _th_add_c_2;
_saxi_flag_5 <= 0;
end
if((th_add == 6) && (4 == 6)) begin
if((th_add == 6) && 0) begin
_saxi_register_6 <= _th_add_c_2;
_saxi_flag_6 <= 0;
end
if((th_add == 6) && (4 == 7)) begin
if((th_add == 6) && 0) begin
_saxi_register_7 <= _th_add_c_2;
_saxi_flag_7 <= 0;
end
if((th_add == 7) && (1 == 0)) begin
if((th_add == 7) && 0) begin
_saxi_register_0 <= 1;
_saxi_flag_0 <= 1;
_saxi_resetval_0 <= 0;
end
if((th_add == 7) && (1 == 1)) begin
if((th_add == 7) && 1) begin
_saxi_register_1 <= 1;
_saxi_flag_1 <= 1;
_saxi_resetval_1 <= 0;
end
if((th_add == 7) && (1 == 2)) begin
if((th_add == 7) && 0) begin
_saxi_register_2 <= 1;
_saxi_flag_2 <= 1;
_saxi_resetval_2 <= 0;
end
if((th_add == 7) && (1 == 3)) begin
if((th_add == 7) && 0) begin
_saxi_register_3 <= 1;
_saxi_flag_3 <= 1;
_saxi_resetval_3 <= 0;
end
if((th_add == 7) && (1 == 4)) begin
if((th_add == 7) && 0) begin
_saxi_register_4 <= 1;
_saxi_flag_4 <= 1;
_saxi_resetval_4 <= 0;
end
if((th_add == 7) && (1 == 5)) begin
if((th_add == 7) && 0) begin
_saxi_register_5 <= 1;
_saxi_flag_5 <= 1;
_saxi_resetval_5 <= 0;
end
if((th_add == 7) && (1 == 6)) begin
if((th_add == 7) && 0) begin
_saxi_register_6 <= 1;
_saxi_flag_6 <= 1;
_saxi_resetval_6 <= 0;
end
if((th_add == 7) && (1 == 7)) begin
if((th_add == 7) && 0) begin
_saxi_register_7 <= 1;
_saxi_flag_7 <= 1;
_saxi_resetval_7 <= 0;
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32 changes: 16 additions & 16 deletions examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipcore.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1551,66 +1551,66 @@
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
_saxi_register_7 <= saxi_wdata;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 0)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
_saxi_register_0 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 1)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_1 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 2)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_2 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 3)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_3 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 4)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_4 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 5)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_5 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 6)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_6 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 7)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_7 <= 0;
end
if((th_memcpy == 28) && (4 == 0)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_0 <= 1;
_saxi_flag_0 <= 1;
_saxi_resetval_0 <= 0;
end
if((th_memcpy == 28) && (4 == 1)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_1 <= 1;
_saxi_flag_1 <= 1;
_saxi_resetval_1 <= 0;
end
if((th_memcpy == 28) && (4 == 2)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_2 <= 1;
_saxi_flag_2 <= 1;
_saxi_resetval_2 <= 0;
end
if((th_memcpy == 28) && (4 == 3)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_3 <= 1;
_saxi_flag_3 <= 1;
_saxi_resetval_3 <= 0;
end
if((th_memcpy == 28) && (4 == 4)) begin
if((th_memcpy == 28) && 1) begin
_saxi_register_4 <= 1;
_saxi_flag_4 <= 1;
_saxi_resetval_4 <= 0;
end
if((th_memcpy == 28) && (4 == 5)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_5 <= 1;
_saxi_flag_5 <= 1;
_saxi_resetval_5 <= 0;
end
if((th_memcpy == 28) && (4 == 6)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_6 <= 1;
_saxi_flag_6 <= 1;
_saxi_resetval_6 <= 0;
end
if((th_memcpy == 28) && (4 == 7)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_7 <= 1;
_saxi_flag_7 <= 1;
_saxi_resetval_7 <= 0;
Expand Down
24 changes: 12 additions & 12 deletions examples/thread_ipcore/test_thread_ipcore.py
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Original file line number Diff line number Diff line change
Expand Up @@ -697,50 +697,50 @@
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
_saxi_register_3 <= saxi_wdata;
end
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 0)) begin
if((_saxi_register_0 == 1) && (th_blink == 2) && 1) begin
_saxi_register_0 <= 0;
end
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 1)) begin
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
_saxi_register_1 <= 0;
end
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 2)) begin
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
_saxi_register_2 <= 0;
end
if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 3)) begin
if((_saxi_register_0 == 1) && (th_blink == 2) && 0) begin
_saxi_register_3 <= 0;
end
if((th_blink == 3) && (3 == 0)) begin
if((th_blink == 3) && 0) begin
_saxi_register_0 <= 0;
_saxi_flag_0 <= 0;
end
if((th_blink == 3) && (3 == 1)) begin
if((th_blink == 3) && 0) begin
_saxi_register_1 <= 0;
_saxi_flag_1 <= 0;
end
if((th_blink == 3) && (3 == 2)) begin
if((th_blink == 3) && 0) begin
_saxi_register_2 <= 0;
_saxi_flag_2 <= 0;
end
if((th_blink == 3) && (3 == 3)) begin
if((th_blink == 3) && 1) begin
_saxi_register_3 <= 0;
_saxi_flag_3 <= 0;
end
if((th_blink == 11) && (3 == 0)) begin
if((th_blink == 11) && 0) begin
_saxi_register_0 <= 1;
_saxi_flag_0 <= 1;
_saxi_resetval_0 <= 0;
end
if((th_blink == 11) && (3 == 1)) begin
if((th_blink == 11) && 0) begin
_saxi_register_1 <= 1;
_saxi_flag_1 <= 1;
_saxi_resetval_1 <= 0;
end
if((th_blink == 11) && (3 == 2)) begin
if((th_blink == 11) && 0) begin
_saxi_register_2 <= 1;
_saxi_flag_2 <= 1;
_saxi_resetval_2 <= 0;
end
if((th_blink == 11) && (3 == 3)) begin
if((th_blink == 11) && 1) begin
_saxi_register_3 <= 1;
_saxi_flag_3 <= 1;
_saxi_resetval_3 <= 0;
Expand Down
32 changes: 16 additions & 16 deletions examples/thread_memcpy_ipcore/test_thread_memcpy_ipcore.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1537,66 +1537,66 @@
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
_saxi_register_7 <= saxi_wdata;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 0)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
_saxi_register_0 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 1)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_1 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 2)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_2 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 3)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_3 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 4)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_4 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 5)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_5 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 6)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_6 <= 0;
end
if((_saxi_register_0 == 1) && (th_memcpy == 2) && (0 == 7)) begin
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 0) begin
_saxi_register_7 <= 0;
end
if((th_memcpy == 28) && (4 == 0)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_0 <= 1;
_saxi_flag_0 <= 1;
_saxi_resetval_0 <= 0;
end
if((th_memcpy == 28) && (4 == 1)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_1 <= 1;
_saxi_flag_1 <= 1;
_saxi_resetval_1 <= 0;
end
if((th_memcpy == 28) && (4 == 2)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_2 <= 1;
_saxi_flag_2 <= 1;
_saxi_resetval_2 <= 0;
end
if((th_memcpy == 28) && (4 == 3)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_3 <= 1;
_saxi_flag_3 <= 1;
_saxi_resetval_3 <= 0;
end
if((th_memcpy == 28) && (4 == 4)) begin
if((th_memcpy == 28) && 1) begin
_saxi_register_4 <= 1;
_saxi_flag_4 <= 1;
_saxi_resetval_4 <= 0;
end
if((th_memcpy == 28) && (4 == 5)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_5 <= 1;
_saxi_flag_5 <= 1;
_saxi_resetval_5 <= 0;
end
if((th_memcpy == 28) && (4 == 6)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_6 <= 1;
_saxi_flag_6 <= 1;
_saxi_resetval_6 <= 0;
end
if((th_memcpy == 28) && (4 == 7)) begin
if((th_memcpy == 28) && 0) begin
_saxi_register_7 <= 1;
_saxi_flag_7 <= 1;
_saxi_resetval_7 <= 0;
Expand Down
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