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@shtaxxx shtaxxx released this 29 Oct 06:19
· 1796 commits to master since this release
0.4.0
87cb5a8

0.4.0 update

  • lib.Pipeline: a library for computation pipeline modeling as a dataflow is added.
  • lib.FSM and lib.FSM: supporting prev() method to access the previous value of a reg.
  • lib.Simulation: finish() method is added.
  • to_verilog: number representation bugs are fixed.
  • vtypes: IntX and IntZ are added. Object dump method str() is implemented for easy debugging. Type check capability is enhanced.
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