Skip to content

0.8.1
Compare
Choose a tag to compare
@shtaxxx shtaxxx released this 07 Apr 14:54
· 1219 commits to master since this release
0.8.1
23b3d96

Update

A portable IP-core synthesis is now supported. You can easily create an original IP-core just by writing Python!

  • AXI-slave interface and memory-mapped register are supported
  • AXI-master in veriloggen.thread supports read/write method to access to a memory-mapped register easily
  • AXI4/Avalon IP-core packager support via IPgen is added
  • Synopsys VCS (very fast commercial Verilog simulator) support is added

Test environment

Mac OSX 10.12.4

  • python 3.6.1
  • python 2.7.13
  • icarus verilog 0.9.7

Ubuntu 16.04

  • python 3.5.2
  • python 2.7.12
  • icarus verilog 0.9.7
Assets 2
Loading