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1.6.0
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@shtaxxx shtaxxx released this 18 Apr 07:31
· 710 commits to master since this release
1.6.0
a5f57fc

Update

  • Bug fix of Repeat operator (veriloggen.core)
  • Bug fix of Shift-Right-Arithmetically operator (veriloggen.thread)
  • Windows support (veriloggen.simulation)
  • All of AXI interface signals are implemented in the AXI-based controllers. To create a complete AXI interface and IP-XACT, IPgen is no longer required. So IPgen is removed from the installation requirements.
  • Updated the license description
  • Added the contribution guideline

Test environment

Mac OSX 10.14.4

  • Python 3.7.3
  • Icarus Verilog 10.2
  • Pyverilog 1.1.4

Ubuntu 18.04.2

  • Python 3.6.7
  • Icarus Verilog 10.1
  • Pyverilog 1.1.4
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