2.1.1

Update

• Bug fix of resolver especially for generate statements.
• resolver.resolve returns optimized modules after the deep-copy of the input modules.
• Updated AXIM to support python-native literal values as the transfer size.

Test environment

macOS 12.6.1 (Apple Silicon M2)

Python 3.10.6

• Icarus Verilog 11.0
• Pyverilog 1.3.0
• numpy 1.23.2
• Jinja2 3.1.2

Ubuntu 20.04.5 (AMD Ryzen 9 5950X)

Python 3.10.6

• Icarus Verilog 10.3
• Pyverilog 1.3.0
• numpy 1.23.4
• Jinja2 3.1.2