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Optim level 2 and 3 modifiy circuits that match topology #3386

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nonhermitian opened this issue Nov 4, 2019 · 2 comments · Fixed by #3391
Closed

Optim level 2 and 3 modifiy circuits that match topology #3386

nonhermitian opened this issue Nov 4, 2019 · 2 comments · Fixed by #3391
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bug Something isn't working priority: high status: pending PR It has one or more PRs pending to solve this issue

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@nonhermitian
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Information

  • Qiskit Terra version: master
  • Python version:
  • Operating system:

What is the current behavior?

The following circuit fits Vigo-like topologies exactly:

Screen Shot 2019-11-04 at 2 35 42 PM

But optimization level 3 gives:

Screen Shot 2019-11-04 at 2 35 56 PM

Where as the default gives the expected original circuit (save for H -> U2):

Screen Shot 2019-11-04 at 2 36 13 PM

Steps to reproduce the problem

qc = QuantumCircuit(5)
qc.h(3)
qc.cx([3, 3, 1, 1], [1, 4, 2, 0])
qc.measure_all()
new_qc = transpile(qc, backend, optimization_level=3)
new_qc.draw(output='mpl')

What is the expected behavior?

Suggested solutions

@nonhermitian nonhermitian added the bug Something isn't working label Nov 4, 2019
@nonhermitian nonhermitian changed the title Optim level 3 modifies circuits that match topology Optim level 2 and 3 modifiy circuits that match topology Nov 4, 2019
@1ucian0 1ucian0 self-assigned this Nov 5, 2019
@1ucian0
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1ucian0 commented Nov 5, 2019

It seems like TrivialLayout was not an attempt before DenseLayout. #3324 could be a solution to this. #3043 is also an option. @ajavadia ?

It's important to notice that neither TrivialLayout nor CSPLayout are noise aware (yet).

@1ucian0
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1ucian0 commented Nov 5, 2019

In PR #3391 I implemented the second approach, using CSPLayout (which resorts to the trivial layout if that's the only possible map).

@1ucian0 1ucian0 added the status: pending PR It has one or more PRs pending to solve this issue label Nov 5, 2019
@mergify mergify bot closed this as completed in #3391 Feb 27, 2020
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