Classical conditioning on individual classical bits now supported #6018

TharrmashasthaPV · 2021-03-13T07:55:15Z

Summary

Fixes #1160 .

Details and comments

Before this PR the classical conditioning of gates only allowed conditioning on classical registers. As a follow up of discussions in #1160 , this PR allows conditioning gates on single classical bits too. Various tests have been included.

Known Issues:

Condition value validation required. Currently only the non-negativity condition of the condition value is checked. So, passing on any float or Boolean (for creg) also get accepted as a valid condition value which is not quite right. Also, bit length of the condition value is also not checked i.e., passing a m bit integer as the condition value for condition on a creg of n classical bits (where m>n) does not raise error .
All the drawers break when trying to draw a circuit that contains gates with classical conditioning on a single cbit.
qc.qasm() breaks when circuit qc contains gates with classical conditioning on a single cbit.
qc.depth() also breaks. Refer to Classical conditioning on individual classical bits now supported #6018 (comment)
disassemble(qc_assembled) breaks where qc_assembled is an assembled Qobj.
qc.num_connected_components breaks.
circuit_to_instruction(qc) breaks.
_check_wires_list() and substitute_node_with_dag() methods in qiskit/dagcircuit/dagcircuit.py break.
_is_same_c_conf() method in ForwardMatch and BackwardMatch classes in qiskit/transpiler/passes/optimization/template_matching breaks.
run() method in ConsolidateBlocks class in qiskit/transpiler/passes/optimization breaks.

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kdk

Thanks @TharrmashasthaPV for taking this on! This looks great so far. A few small comments inline.

Can you open separate issues for validation of the condition values and for raising gracefully when attempting to export to QASM2?

qiskit/assembler/assemble_circuits.py

qiskit/circuit/instruction.py

qiskit/dagcircuit/dagcircuit.py

kdk · 2021-04-23T21:17:35Z

qiskit/dagcircuit/dagcircuit.py

+                        except StopIteration as ex:
+                            raise DAGCircuitError('Did not find creg containing '
+                                                  'mapped clbit in conditional.') from ex


A nice generalization that's enabled by this PR (and maybe something to consider for a future issue/contribution) is to allow conditionals that span a list of arbitrary circuit Clbits (even if they live in different Registers). That would allow us to remove this DAGCircuitError (in the case where the condition doesn't map cleanly to a different register) and instead map the condition to a list of Clbits.

So we ( me and @1ucian0 ) have been thinking about the generalization: conditioning on a list of Clbits. I would certainly be happy to work on it.

1ucian0 · 2021-04-30T08:24:05Z

qiskit/dagcircuit/dagcircuit.py

@@ -351,12 +352,19 @@ def _bits_in_condition(self, cond):
        """Return a list of bits in the given condition.

        Args:
-            cond (tuple or None): optional condition (ClassicalRegister, int)
+            cond (tuple or None): optional condition (ClassicalRegister, int) or (Clbit, int)


Suggested change

cond (tuple or None): optional condition (ClassicalRegister, int) or (Clbit, int)

cond (tuple or None): optional condition (ClassicalRegister, int), (Clbit, int), or (Clbit, bool)

1ucian0 · 2021-04-30T08:24:37Z

qiskit/dagcircuit/dagcircuit.py

@@ -320,13 +320,14 @@ def _check_condition(self, name, condition):

        Args:
            name (string): used for error reporting
-            condition (tuple or None): a condition tuple (ClassicalRegister,int)
+            condition (tuple or None): a condition tuple (ClassicalRegister,int),
+              (Clbit,Bool) or (Clbit,int)


Suggested change

(Clbit,Bool) or (Clbit,int)

(Clbit, bool) or (Clbit, int)

kdk

Thanks for taking this on @TharrmashasthaPV , this looks great! Is there a release note covering this in any of the PRs? If not, it'd be good to add one here.

TharrmashasthaPV · 2021-05-21T05:10:41Z

Thanks for taking this on @TharrmashasthaPV , this looks great! Is there a release note covering this in any of the PRs? If not, it'd be good to add one here.

Thanks a lot for the review @kdk . I have not added a release note yet. I will be sure to add one.

…xissue1160

kdk

Thanks @TharrmashasthaPV !

In Qiskit#6018 initial support for adding classical conditions on a single bit instead of a register was added. However this wasn't accounted for in qpy because it didn't exist when qpy was first written. This commit adds support to qpy without a file format change so it can be backported and used with already released versions of qpy without needing a new format version. This is accomplished by exploiting the strict register naming in qiskit. A register can't have a name outside of regex "[a-z][a-zA-Z0-9_]*" which we leverage in the case of single clbit conditions the "register" name in the output QPY data is set to str(clbit_index) which isn't a valid name. Then on the loading side we check for a valid name, if it's outside the allowed regex we treat the condition as a single bit and the name is a str(index). The tradeoff here is that for a QPY file generated with 0.18.1 (assuming this is backported and included in 0.18.1) this qpy file can not be loaded with qiskit 0.18.0. But this is fine as we only guarantee compatibility in one direction (loading qpy files generated with older with qiskit with a newer version of qiskit). Fixes partially Qiskit#6475

* Handle single bit conditions in QPY In #6018 initial support for adding classical conditions on a single bit instead of a register was added. However this wasn't accounted for in qpy because it didn't exist when qpy was first written. This commit adds support to qpy without a file format change so it can be backported and used with already released versions of qpy without needing a new format version. This is accomplished by exploiting the strict register naming in qiskit. A register can't have a name outside of regex "[a-z][a-zA-Z0-9_]*" which we leverage in the case of single clbit conditions the "register" name in the output QPY data is set to str(clbit_index) which isn't a valid name. Then on the loading side we check for a valid name, if it's outside the allowed regex we treat the condition as a single bit and the name is a str(index). The tradeoff here is that for a QPY file generated with 0.18.1 (assuming this is backported and included in 0.18.1) this qpy file can not be loaded with qiskit 0.18.0. But this is fine as we only guarantee compatibility in one direction (loading qpy files generated with older with qiskit with a newer version of qiskit). Fixes partially #6475 * Add release note * Prefix bit index with null character This commit modifies the special string we use in the register name field to be prefixed with a null character. This leaves open using the string for other special cases and also returning a sane error if an invalid QPY file was generated by something besides Qiskit. * Update qiskit/circuit/qpy_serialization.py Co-authored-by: Jake Lishman <jake@binhbar.com> * Add note to release note about feature not being supported * Add backwards compat test case too Co-authored-by: Jake Lishman <jake@binhbar.com> Co-authored-by: Jake Lishman <jake.lishman@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Handle single bit conditions in QPY In #6018 initial support for adding classical conditions on a single bit instead of a register was added. However this wasn't accounted for in qpy because it didn't exist when qpy was first written. This commit adds support to qpy without a file format change so it can be backported and used with already released versions of qpy without needing a new format version. This is accomplished by exploiting the strict register naming in qiskit. A register can't have a name outside of regex "[a-z][a-zA-Z0-9_]*" which we leverage in the case of single clbit conditions the "register" name in the output QPY data is set to str(clbit_index) which isn't a valid name. Then on the loading side we check for a valid name, if it's outside the allowed regex we treat the condition as a single bit and the name is a str(index). The tradeoff here is that for a QPY file generated with 0.18.1 (assuming this is backported and included in 0.18.1) this qpy file can not be loaded with qiskit 0.18.0. But this is fine as we only guarantee compatibility in one direction (loading qpy files generated with older with qiskit with a newer version of qiskit). Fixes partially #6475 * Add release note * Prefix bit index with null character This commit modifies the special string we use in the register name field to be prefixed with a null character. This leaves open using the string for other special cases and also returning a sane error if an invalid QPY file was generated by something besides Qiskit. * Update qiskit/circuit/qpy_serialization.py Co-authored-by: Jake Lishman <jake@binhbar.com> * Add note to release note about feature not being supported * Add backwards compat test case too Co-authored-by: Jake Lishman <jake@binhbar.com> Co-authored-by: Jake Lishman <jake.lishman@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit afb0c47)

* Handle single bit conditions in QPY In #6018 initial support for adding classical conditions on a single bit instead of a register was added. However this wasn't accounted for in qpy because it didn't exist when qpy was first written. This commit adds support to qpy without a file format change so it can be backported and used with already released versions of qpy without needing a new format version. This is accomplished by exploiting the strict register naming in qiskit. A register can't have a name outside of regex "[a-z][a-zA-Z0-9_]*" which we leverage in the case of single clbit conditions the "register" name in the output QPY data is set to str(clbit_index) which isn't a valid name. Then on the loading side we check for a valid name, if it's outside the allowed regex we treat the condition as a single bit and the name is a str(index). The tradeoff here is that for a QPY file generated with 0.18.1 (assuming this is backported and included in 0.18.1) this qpy file can not be loaded with qiskit 0.18.0. But this is fine as we only guarantee compatibility in one direction (loading qpy files generated with older with qiskit with a newer version of qiskit). Fixes partially #6475 * Add release note * Prefix bit index with null character This commit modifies the special string we use in the register name field to be prefixed with a null character. This leaves open using the string for other special cases and also returning a sane error if an invalid QPY file was generated by something besides Qiskit. * Update qiskit/circuit/qpy_serialization.py Co-authored-by: Jake Lishman <jake@binhbar.com> * Add note to release note about feature not being supported * Add backwards compat test case too Co-authored-by: Jake Lishman <jake@binhbar.com> Co-authored-by: Jake Lishman <jake.lishman@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit afb0c47) Co-authored-by: Matthew Treinish <mtreinish@kortar.org>

1ucian0 · 2021-09-06T15:05:35Z

Hi @TharrmashasthaPV
How far is this of pending things doing? Do you mind PRing a single release note once that the feature is fully supported?

TharrmashasthaPV and others added 13 commits March 13, 2021 12:35

Cbit conditional

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Merge branch 'master' into fixissue1160

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Merge branch 'master' of https://github.com/TharrmashasthaPV/qiskit-t…

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lint fixed

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lint-fix

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added extra test

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TharrmashasthaPV marked this pull request as ready for review March 31, 2021 18:53

TharrmashasthaPV requested a review from a team as a code owner March 31, 2021 18:53

TharrmashasthaPV changed the title ~~[WIP] Classical conditioning on individual classical bits now supported~~ Classical conditioning on individual classical bits now supported Apr 7, 2021

Merge branch 'master' of https://github.com/TharrmashasthaPV/qiskit-t…

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1ucian0 self-assigned this Apr 9, 2021

TharrmashasthaPV added 2 commits April 16, 2021 13:04

Merge branch 'master' of https://github.com/TharrmashasthaPV/qiskit-t…

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unwanted comment removed

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This was referenced Apr 16, 2021

Single bit conditioning support for registerless circuits #6244

Merged

Latex drawer extended for drawing circuits with single classical bit conditioning #6248

Merged

refactored for bit.register deprication

bb55831

TharrmashasthaPV mentioned this pull request Apr 20, 2021

MPL drawer extended for drawing circuits with single classical bit conditioning #6259

Merged

Merge branch 'master' of upstream Qiskit into fixissue1160

1fb38e3

TharrmashasthaPV mentioned this pull request Apr 20, 2021

Text drawer extended for drawing circuits with single classical bit conditioning #6261

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kdk reviewed Apr 23, 2021

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fixed some recommended changes

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1ucian0 reviewed Apr 30, 2021

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1ucian0 and others added 2 commits May 13, 2021 07:39

Merge branch 'main' of github.com:Qiskit/qiskit-terra into fixissue1160

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Merge branch 'main' into fixissue1160

3842dec

kdk added the Changelog: New Feature Include in the "Added" section of the changelog label May 19, 2021

kdk reviewed May 19, 2021

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TharrmashasthaPV and others added 3 commits May 21, 2021 10:40

Merge branch 'main' into fixissue1160

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Merge branch 'main' of https://github.com/Qiskit/qiskit-terra into fi…

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…xissue1160

Added reno

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kdk approved these changes May 24, 2021

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Merge branch 'main' into fixissue1160

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kdk added the automerge label May 24, 2021

mergify bot merged commit 9f28ad7 into Qiskit:main May 25, 2021

This was referenced May 28, 2021

Single classical bit conditioning breaks various functions #6475

Open

Fixed error in qc.depth() when using on circuits with single bit classical conditions #6476

Merged

TharrmashasthaPV mentioned this pull request Jun 12, 2021

Fixed qc.num_connected_components() for circuits with bit conditioned gates #6564

Merged

This was referenced Jun 15, 2021

Flattened conditional circuits give incorrect results #6583

Closed

Cannot convert condition in circuit with multiple classical registers to instruction #6584

Closed

mtreinish mentioned this pull request Jul 9, 2021

Add back held release notes from 0.18.0 #6715

Closed

TharrmashasthaPV mentioned this pull request Jul 17, 2021

[WIP] Support for classical conditioning of gates on a list of classical bits #6761

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jgermain48 mentioned this pull request Jul 19, 2021

Seeing issue like previously closed on #6018 #6769

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mtreinish mentioned this pull request Jul 20, 2021

Handle single bit conditions in QPY #6775

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TharrmashasthaPV mentioned this pull request Sep 15, 2021

Fixed diassembler for circuits containing single bit conditioned gates #6989

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Classical conditioning on individual classical bits now supported #6018

Classical conditioning on individual classical bits now supported #6018

TharrmashasthaPV commented Mar 13, 2021 •

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TharrmashasthaPV commented May 21, 2021

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1ucian0 commented Sep 6, 2021

	cond (tuple or None): optional condition (ClassicalRegister, int) or (Clbit, int)
	cond (tuple or None): optional condition (ClassicalRegister, int), (Clbit, int), or (Clbit, bool)

Classical conditioning on individual classical bits now supported #6018

Classical conditioning on individual classical bits now supported #6018

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TharrmashasthaPV commented Mar 13, 2021 • edited Loading

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