Combine circuits with clbits onto those with none

qiskit/circuit/quantumcircuit.py

@@ -823,6 +823,13 @@ def compose(
         else:
             dest = self.copy()
 
+        # If self does not have any cregs but other does then we allow
+        # that and add the registers to the output dest
+        if isinstance(other, QuantumCircuit):
+            if not self.clbits and other.clbits:
+                for reg in other.cregs:
+                    dest.add_register(reg)
+
         if wrap:
             try:
                 other = other.to_gate()
@@ -847,15 +854,14 @@ def compose(
 
         instrs = other.data
 
-        if other.num_qubits > self.num_qubits or other.num_clbits > self.num_clbits:
+        if other.num_qubits > dest.num_qubits or other.num_clbits > dest.num_clbits:
             raise CircuitError(
                 "Trying to compose with another QuantumCircuit which has more 'in' edges."
             )
 
         # number of qubits and clbits must match number in circuit or None
-        identity_qubit_map = dict(zip(other.qubits, self.qubits))
-        identity_clbit_map = dict(zip(other.clbits, self.clbits))
-
+        identity_qubit_map = dict(zip(other.qubits, dest.qubits))
+        identity_clbit_map = dict(zip(other.clbits, dest.clbits))
         if qubits is None:
             qubit_map = identity_qubit_map
         elif len(qubits) != len(other.qubits):

test/python/circuit/test_compose.py

@@ -25,8 +25,9 @@
     Parameter,
     Gate,
     Instruction,
+    Clbit,
 )
-from qiskit.circuit.library import HGate, RZGate, CXGate, CCXGate
+from qiskit.circuit.library import HGate, RZGate, CXGate, CCXGate, TwoLocal
 from qiskit.test import QiskitTestCase
 
 
@@ -592,6 +593,42 @@ def test_wrapping_unitary_circuit(self):
             qc = qc_init.compose(qc_nonunitary, wrap=True)
             self.assertIsInstance(qc.data[1][0], Instruction)
 
+    def test_compose_no_clbits_in_one(self):
+        """Test combining a circuit with cregs to one without"""
+        ansatz = TwoLocal(2, rotation_blocks="ry", entanglement_blocks="cx")
+
+        qc = QuantumCircuit(2)
+        qc.measure_all()
+        out = ansatz.compose(qc)
+        self.assertEqual(
+            out.clbits,
+            [Clbit(ClassicalRegister(2, "meas"), 0), Clbit(ClassicalRegister(2, "meas"), 1)],
+        )
+
+    def test_compose_no_clbits_in_one_inplace(self):
+        """Test combining a circuit with cregs to one without inplace"""
+        ansatz = TwoLocal(2, rotation_blocks="ry", entanglement_blocks="cx")
+
+        qc = QuantumCircuit(2)
+        qc.measure_all()
+        ansatz.compose(qc, inplace=True)
+        self.assertEqual(
+            ansatz.clbits,
+            [Clbit(ClassicalRegister(2, "meas"), 0), Clbit(ClassicalRegister(2, "meas"), 1)],
+        )
+
+    def test_compose_no_clbits_in_one_multireg(self):
+        """Test combining a circuit with cregs to one without, multi cregs"""
+        ansatz = TwoLocal(2, rotation_blocks="ry", entanglement_blocks="cx")
+
+        qa = QuantumRegister(2, "q")
+        ca = ClassicalRegister(2, "a")
+        cb = ClassicalRegister(2, "b")
+        qc = QuantumCircuit(qa, ca, cb)
+        qc.measure(0, cb[1])
+        out = ansatz.compose(qc)
+        self.assertEqual(out.cregs, qc.cregs)
+
 
 if __name__ == "__main__":
     unittest.main()