cpu/sam0: merge GPIO driver

Signed-off-by: dylad <dylan.laduranty@mesotic.com>
RIOT-OS · Sep 4, 2017 · 12acbfe · 12acbfe
1 parent 1809a1d
commit 12acbfe
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Showing 4 changed files with 63 additions and 264 deletions.
diff --git a/cpu/saml21/periph/gpio.c → cpu/sam0_common/periph/gpio.c b/cpu/saml21/periph/gpio.c → cpu/sam0_common/periph/gpio.c
@@ -9,7 +9,7 @@
  */
 
 /**
- * @ingroup     cpu_saml21
+ * @ingroup     cpu_sam0_common
  * @ingroup     drivers_periph_gpio
  * @{
  *
@@ -26,6 +26,7 @@
 
 #include "cpu.h"
 #include "periph/gpio.h"
+#include "periph_conf.h"
 
 #define ENABLE_DEBUG (0)
 #include "debug.h"
@@ -40,19 +41,8 @@
  */
 #define MODE_PINCFG_MASK            (0x06)
 
-/**
- * @brief   Mapping of pins to EXTI lines, -1 means not EXTI possible
- */
-static const int8_t exti_config[2][32] = {
-    { 0,  1,  2,  3,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
-      0,  1,  2,  3,  4,  5,  6,  7, 12, 13, -1, 15, -1, -1, 10, 11},
-    { 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
-      0,  1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1, -1, -1, 14, 15},
-};
-
 static gpio_isr_ctx_t gpio_config[NUMOF_IRQS];
 
-
 static inline PortGroup *_port(gpio_t pin)
 {
     return (PortGroup *)(pin & ~(0x1f));
@@ -128,30 +118,44 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     if (exti == -1) {
         return -1;
     }
-
+#if CPU_FAM_SAML21
+    /* disable the EIC module*/
+    EIC->CTRLA.reg = 0;
+    while (EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}
+#endif
     /* save callback */
     gpio_config[exti].cb = cb;
     gpio_config[exti].arg = arg;
     /* configure pin as input and set MUX to peripheral function A */
     gpio_init(pin, mode);
     gpio_init_mux(pin, GPIO_MUX_A);
-    /* enable clocks for the EIC module */
-    MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
-    GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
-    /* disable the EIC module*/
-    EIC->CTRLA.reg = 0;
-    while (EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}
     /* configure the active flank */
     EIC->CONFIG[exti >> 3].reg &= ~(0xf << ((exti & 0x7) * 4));
     EIC->CONFIG[exti >> 3].reg |=  (flank << ((exti & 0x7) * 4));
     /* enable the global EIC interrupt */
     NVIC_EnableIRQ(EIC_IRQn);
-    /*Enable pin interrupt */
+    /* clear interrupt flag and enable the interrupt line and line wakeup */
     EIC->INTFLAG.reg = (1 << exti);
     EIC->INTENSET.reg = (1 << exti);
+#if CPU_FAM_SAMD21
+    EIC->WAKEUP.reg |= (1 << exti);
+    /* enable clocks for the EIC module */
+    PM->APBAMASK.reg |= PM_APBAMASK_EIC;
+    GCLK->CLKCTRL.reg = (EIC_GCLK_ID |
+                         GCLK_CLKCTRL_CLKEN |
+                         GCLK_CLKCTRL_GEN_GCLK2);
+    while (GCLK->STATUS.bit.SYNCBUSY) {}
+    /* enable the EIC module*/
+    EIC->CTRL.reg = EIC_CTRL_ENABLE;
+    while (EIC->STATUS.reg & EIC_STATUS_SYNCBUSY) {}
+#else /* cpu_saml21 */
+    /* enable clocks for the EIC module */
+    MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+    GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
     /* enable the EIC module*/
     EIC->CTRLA.reg = EIC_CTRLA_ENABLE;
     while (EIC->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) {}
+#endif
     return 0;
 }
 

diff --git a/cpu/samd21/include/periph_cpu.h b/cpu/samd21/include/periph_cpu.h
@@ -28,6 +28,35 @@
 extern "C" {
 #endif
 
+/**
+ * @brief   Mapping of pins to EXTI lines, -1 means not EXTI possible
+ */
+static const int8_t exti_config[2][32] = {
+#ifdef CPU_MODEL_SAMD21J18A
+    { 0,  1,  2,  3,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
+      0,  1,  2,  3,  4,  5,  6,  7, 12, 13, -1, 15,  8, -1, 10, 11},
+    { 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
+      0,  1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1, -1, -1, 14, 15},
+#elif CPU_MODEL_SAMD21G18A
+    { 0,  1,  2,  3,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
+      0,  1,  2,  3,  4,  5,  6,  7, 12, 13, -1, 15,  8, -1, 10, 11},
+    {-1, -1,  2,  3, -1, -1, -1, -1,  8,  9, 10, 11, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1, -1, -1, -1, -1},
+#elif CPU_MODEL_SAMR21G18A
+    {-1,  1, -1, -1,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
+     -1,  1,  2,  3, -1, -1,  6,  7, 12, 13, -1, 15,  8, -1, 10, 11},
+    { 0, -1,  2,  3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+      0,  1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1,  8, -1, -1, -1},
+#elif CPU_MODEL_SAMR21E18A
+    {-1, -1, -1, -1, -1, -1,  6,  7, -1,  9, 10, 11, -1, -1, 14, 15,
+     -1,  1,  2,  3, -1, -1, -1, -1, 12, 13, -1, 15,  8, -1, 10, 11},
+    { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+      0,  1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},
+#else
+    #error Please define a proper CPU_MODEL.
+#endif
+};
+
 /**
  * @brief   Available ports on the SAMD21
  */

diff --git a/cpu/samd21/periph/gpio.c b/cpu/samd21/periph/gpio.c
diff --git a/cpu/saml21/include/periph_cpu.h b/cpu/saml21/include/periph_cpu.h
@@ -26,6 +26,16 @@
 extern "C" {
 #endif
 
+/**
+ * @brief   Mapping of pins to EXTI lines, -1 means not EXTI possible
+ */
+static const int8_t exti_config[2][32] = {
+    { 0,  1,  2,  3,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
+      0,  1,  2,  3,  4,  5,  6,  7, 12, 13, -1, 15, -1, -1, 10, 11},
+    { 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
+      0,  1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1, -1, -1, 14, 15},
+};
+
 /**
  * @brief   Available ports on the SAML21 for convenient access
  */