cpu/stm32: Implement periph/gpio_ll{,_irq} except for STM32F1

Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
RIOT-OS · Apr 22, 2022 · 48d3224 · 48d3224
1 parent 7e63216
commit 48d3224
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Showing 21 changed files with 838 additions and 2 deletions.
diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features
@@ -12,6 +12,13 @@ FEATURES_PROVIDED += periph_rtt_overflow
 FEATURES_PROVIDED += periph_uart_modecfg
 FEATURES_PROVIDED += periph_uart_nonblocking
 
+ifneq ($(CPU_FAM),f1)
+  FEATURES_PROVIDED += periph_gpio_ll
+  FEATURES_PROVIDED += periph_gpio_ll_irq
+  FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
+  FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
+endif
+
 ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
   FEATURES_PROVIDED += periph_flashpage
   FEATURES_PROVIDED += periph_flashpage_in_address_space

diff --git a/cpu/stm32/include/gpio_ll_arch.h b/cpu/stm32/include/gpio_ll_arch.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2016 Freie Universität Berlin
+ *               2017 OTA keys S.A.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @ingroup         drivers_periph_gpio_ll
+ * @{
+ *
+ * @file
+ * @brief           CPU specific part of the Peripheral GPIO Low-Level API
+ *
+ * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author          Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef GPIO_LL_ARCH_H
+#define GPIO_LL_ARCH_H
+
+#include "architecture.h"
+#include "periph/gpio_ll.h"
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
+
+/**
+ * @brief   Get a GPIO port by number
+ */
+#if defined(CPU_FAM_STM32MP1)
+#define GPIO_PORT(num)      (GPIOA_BASE + ((num) << 12))
+#else
+#define GPIO_PORT(num)      (GPIOA_BASE + ((num) << 10))
+#endif
+
+/**
+ * @brief   Get a GPIO port number by gpio_t value
+ */
+#if defined(CPU_FAM_STM32MP1)
+#define GPIO_PORT_NUM(port) (((port) - GPIOA_BASE) >> 12)
+#else
+#define GPIO_PORT_NUM(port) (((port) - GPIOA_BASE) >> 10)
+#endif
+
+static inline uword_t gpio_ll_read(gpio_port_t port)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    return p->IDR;
+}
+
+static inline uword_t gpio_ll_read_output(gpio_port_t port)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    return p->ODR;
+}
+
+static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    p->BSRR = mask;
+}
+
+static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    p->BSRR = mask << 16;
+}
+
+static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    unsigned irq_state = irq_disable();
+    p->ODR ^= mask;
+    irq_restore(irq_state);
+}
+
+static inline void gpio_ll_write(gpio_port_t port, uword_t value)
+{
+    GPIO_TypeDef *p = (GPIO_TypeDef *)port;
+    p->ODR = value;
+}
+
+static inline gpio_port_t gpio_get_port(gpio_t pin)
+{
+    return pin & 0xfffffff0LU;
+}
+
+static inline uint8_t gpio_get_pin_num(gpio_t pin)
+{
+    return pin & 0xfLU;
+}
+
+static inline gpio_port_t gpio_port_pack_addr(void *addr)
+{
+    return (gpio_port_t)addr;
+}
+
+static inline void * gpio_port_unpack_addr(gpio_port_t port)
+{
+    if (port < GPIOA_BASE) {
+        return (void *)port;
+    }
+
+    return NULL;
+}
+
+static inline bool is_gpio_port_num_valid(uint_fast8_t num)
+{
+    switch (num) {
+    default:
+        return false;
+#ifdef GPIOA_BASE
+    case 0:
+#endif
+#ifdef GPIOB_BASE
+    case 1:
+#endif
+#ifdef GPIOC_BASE
+    case 2:
+#endif
+#ifdef GPIOD_BASE
+    case 3:
+#endif
+#ifdef GPIOE_BASE
+    case 4:
+#endif
+#ifdef GPIOF_BASE
+    case 5:
+#endif
+#ifdef GPIOG_BASE
+    case 6:
+#endif
+#ifdef GPIOH_BASE
+    case 7:
+#endif
+#ifdef GPIOI_BASE
+    case 8:
+#endif
+#ifdef GPIOJ_BASE
+    case 9:
+#endif
+#ifdef GPIOK_BASE
+    case 10:
+#endif
+#ifdef GPIOL_BASE
+    case 11:
+#endif
+#ifdef GPIOM_BASE
+    case 12:
+#endif
+#ifdef GPION_BASE
+    case 13:
+#endif
+#ifdef GPIOO_BASE
+    case 14:
+#endif
+#ifdef GPIOP_BASE
+    case 15:
+#endif
+#ifdef GPIOQ_BASE
+    case 16:
+#endif
+#ifdef GPIOR_BASE
+    case 17:
+#endif
+#ifdef GPIOS_BASE
+    case 18:
+#endif
+#ifdef GPIOT_BASE
+    case 19:
+#endif
+#ifdef GPIOU_BASE
+    case 20:
+#endif
+#ifdef GPIOV_BASE
+    case 21:
+#endif
+#ifdef GPIOW_BASE
+    case 22:
+#endif
+#ifdef GPIOX_BASE
+    case 23:
+#endif
+#ifdef GPIOY_BASE
+    case 24:
+#endif
+#ifdef GPIOZ_BASE
+    case 25:
+#endif
+    return true;
+    }
+}
+
+#endif /* DOXYGEN */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_LL_ARCH_H */
+/** @} */
diff --git a/cpu/stm32/include/periph/cpu_gpio_ll.h b/cpu/stm32/include/periph/cpu_gpio_ll.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2021 Otto-von-Guericke-Universität Magdeburg
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           GPIO LL CPU definitions for the STM32 family
+ *
+ * @author          Marian Buschsieweke <marian.buschsieweke@ovgu.de>
+ */
+
+#ifndef PERIPH_CPU_GPIO_LL_H
+#define PERIPH_CPU_GPIO_LL_H
+
+#include <stdint.h>
+#include "cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hide this from Doxygen to avoid merging implementation details into
+ * public view on type */
+#ifndef DOXYGEN
+
+#define HAVE_GPIO_PULL_STRENGTH_T
+typedef enum {
+    GPIO_PULL_WEAKEST = 0,
+    GPIO_PULL_WEAK = 0,
+    GPIO_PULL_STRONG = 0,
+    GPIO_PULL_STRONGEST = 0
+} gpio_pull_strength_t;
+
+#define HAVE_GPIO_DRIVE_STRENGTH_T
+typedef enum {
+    GPIO_DRIVE_WEAKEST = 0,
+    GPIO_DRIVE_WEAK = 0,
+    GPIO_DRIVE_STRONG = 0,
+    GPIO_DRIVE_STRONGEST = 0
+} gpio_drive_strength_t;
+
+#define HAVE_GPIO_IRQ_TRIG_T
+/*
+ * Layout:
+ *      7 6 5 4 3 2 1 0
+ *      +-+-+-+-+-+-+-+-+
+ *      |   RFU   |T|L|H|
+ *      +-+-+-+-+-+-+-+-+
+ *
+ * RFU = Reserved for future use
+ * T   = Trigger mode (1 = Level triggered, 0 = Edge triggered)
+ * L   = Low (1 = low level / falling edge)
+ * H   = High (1 = high level / rising edge)
+ *
+ * Note: This layout overlaps with gpio_flank_t by intent
+ */
+typedef enum {
+    GPIO_TRIGGER_EDGE_RISING    = 0x1,
+    GPIO_TRIGGER_EDGE_FALLING   = 0x2,
+    GPIO_TRIGGER_EDGE_BOTH      = GPIO_TRIGGER_EDGE_RISING | GPIO_TRIGGER_EDGE_FALLING,
+    GPIO_TRIGGER_LEVEL          = 0x4,
+    GPIO_TRIGGER_LEVEL_HIGH     = GPIO_TRIGGER_LEVEL | GPIO_TRIGGER_EDGE_RISING,
+    GPIO_TRIGGER_LEVEL_LOW      = GPIO_TRIGGER_LEVEL | GPIO_TRIGGER_EDGE_FALLING,
+} gpio_irq_trig_t;
+
+#endif /* ndef Doxygen */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CPU_GPIO_LL_H */
+/** @} */
diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h
@@ -63,6 +63,7 @@
 #include "periph/cpu_dma.h"
 #include "periph/cpu_eth.h"
 #include "periph/cpu_gpio.h"
+#include "periph/cpu_gpio_ll.h"
 #include "periph/cpu_i2c.h"
 #include "periph/cpu_ltdc.h"
 #include "periph/cpu_pm.h"

diff --git a/cpu/stm32/kconfigs/f0/Kconfig b/cpu/stm32/kconfigs/f0/Kconfig
@@ -17,6 +17,10 @@ config CPU_FAM_F0
     select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
     select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_WDT
     select HAS_BOOTLOADER_STM32
 

diff --git a/cpu/stm32/kconfigs/f2/Kconfig b/cpu/stm32/kconfigs/f2/Kconfig
@@ -13,6 +13,10 @@ config CPU_FAM_F2
     select HAS_CPU_STM32F2
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_HWRNG
     select HAS_PERIPH_RTC_MEM
     select HAS_PERIPH_VBAT

diff --git a/cpu/stm32/kconfigs/f3/Kconfig b/cpu/stm32/kconfigs/f3/Kconfig
@@ -14,6 +14,10 @@ config CPU_FAM_F3
     select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
     select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_RTC_MEM
     select HAS_PERIPH_VBAT
     select HAS_PERIPH_WDT

diff --git a/cpu/stm32/kconfigs/f4/Kconfig b/cpu/stm32/kconfigs/f4/Kconfig
@@ -12,6 +12,10 @@ config CPU_FAM_F4
     select HAS_CPU_STM32F4
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_RTC_MEM
     select HAS_PERIPH_VBAT
     select HAS_PERIPH_WDT

diff --git a/cpu/stm32/kconfigs/f7/Kconfig b/cpu/stm32/kconfigs/f7/Kconfig
@@ -13,6 +13,10 @@ config CPU_FAM_F7
     select HAS_CPU_STM32F7
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_HWRNG
     select HAS_PERIPH_RTC_MEM
     select HAS_PERIPH_VBAT

diff --git a/cpu/stm32/kconfigs/g0/Kconfig b/cpu/stm32/kconfigs/g0/Kconfig
@@ -14,6 +14,10 @@ config CPU_FAM_G0
     select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
     select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_VBAT
     select HAS_PERIPH_WDT
     select HAS_BOOTLOADER_STM32

diff --git a/cpu/stm32/kconfigs/g4/Kconfig b/cpu/stm32/kconfigs/g4/Kconfig
@@ -14,6 +14,10 @@ config CPU_FAM_G4
     select HAS_PERIPH_FLASHPAGE
     select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
     select HAS_PERIPH_FLASHPAGE_PAGEWISE
+    select HAS_PERIPH_GPIO_LL
+    select HAS_PERIPH_GPIO_LL_IRQ
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
+    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
     select HAS_PERIPH_HWRNG
     select HAS_PERIPH_VBAT
     select HAS_PERIPH_WDT