cpu/samd5x: add support for FDPLL1 running at 200MHz

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
RIOT-OS · May 16, 2023 · 6607ed1 · 6607ed1
1 parent f790d9f
commit 6607ed1
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Showing 2 changed files with 8 additions and 1 deletion.
diff --git a/cpu/samd5x/cpu.c b/cpu/samd5x/cpu.c
@@ -254,7 +254,11 @@ void sam0_gclk_enable(uint8_t id)
         } else if (USE_XOSC) {
             gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
         }
-
+        break;
+    case SAM0_GCLK_200MHZ:
+        fdpll_init_nolock(1, MHZ(200), OSCCTRL_DPLLCTRLA_ONDEMAND);
+        gclk_connect(SAM0_GCLK_200MHZ, GCLK_SOURCE_DPLL1, 0);
+        fdpll_lock(1);
         break;
     }
 }
@@ -277,6 +281,8 @@ uint32_t sam0_gclk_freq(uint8_t id)
             assert(0);
             return 0;
         }
+    case SAM0_GCLK_200MHZ:
+        return MHZ(200);
     default:
         return 0;
     }

diff --git a/cpu/samd5x/include/periph_cpu.h b/cpu/samd5x/include/periph_cpu.h
@@ -65,6 +65,7 @@ enum {
     SAM0_GCLK_32KHZ,                    /**< 32 kHz clock             */
     SAM0_GCLK_TIMER,                    /**< 4-8 MHz clock for xTimer */
     SAM0_GCLK_PERIPH,                   /**< 12-48 MHz (DFLL) clock   */
+    SAM0_GCLK_200MHZ,                   /**< 200MHz FDPLL clock       */
 };
 /** @} */