cpu/stm32_common: update spi driver with new strategy

RIOT-OS · May 20, 2019 · 7b80718 · 7b80718
1 parent 3a7a6aa
commit 7b80718
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Showing 2 changed files with 20 additions and 18 deletions.
diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h
@@ -472,11 +472,6 @@ typedef struct {
     gpio_t miso_pin;        /**< MISO pin */
     gpio_t sclk_pin;        /**< SCLK pin */
     gpio_t cs_pin;          /**< HWCS pin, set to GPIO_UNDEF if not mapped */
-#ifdef MODULE_PERIPH_SPI_GPIO_MODE
-    gpio_mode_t mosi_pin_mode;  /**< MOSI pin ouput custom mode */
-    gpio_mode_t miso_pin_mode;  /**< MISO pin ouput custom mode */
-    gpio_mode_t sclk_pin_mode;  /**< SCLK pin ouput custom mode */
-#endif
 #ifndef CPU_FAM_STM32F1
     gpio_af_t af;           /**< pin alternate function */
 #endif

diff --git a/cpu/stm32_common/periph/spi.c b/cpu/stm32_common/periph/spi.c
@@ -32,16 +32,6 @@
 #include "periph/spi.h"
 #include "pm_layered.h"
 
-#ifdef MODULE_PERIPH_SPI_GPIO_MODE
-#define MOSI_GPIO_OUT_MODE  (spi_config[bus].mosi_pin_mode)
-#define MISO_GPIO_IN_MODE   (spi_config[bus].miso_pin_mode)
-#define SCLK_GPIO_OUT_MODE  (spi_config[bus].sclk_pin_mode)
-#else
-#define MOSI_GPIO_OUT_MODE  (GPIO_OUT)
-#define MISO_GPIO_IN_MODE   (GPIO_IN)
-#define SCLK_GPIO_OUT_MODE  (GPIO_OUT)
-#endif
-
 /**
  * @brief   Number of bits to shift the BR value in the CR1 register
  */
@@ -88,9 +78,9 @@ void spi_init_pins(spi_t bus)
     gpio_init_af(spi_config[bus].mosi_pin, GPIO_AF_OUT_PP);
     gpio_init(spi_config[bus].miso_pin, GPIO_IN);
 #else
-    gpio_init(spi_config[bus].mosi_pin, MOSI_GPIO_OUT_MODE);
-    gpio_init(spi_config[bus].miso_pin, MISO_GPIO_IN_MODE);
-    gpio_init(spi_config[bus].sclk_pin, SCLK_GPIO_OUT_MODE);
+    gpio_init(spi_config[bus].mosi_pin, GPIO_OUT);
+    gpio_init(spi_config[bus].miso_pin, GPIO_IN);
+    gpio_init(spi_config[bus].sclk_pin, GPIO_OUT);
     gpio_init_af(spi_config[bus].mosi_pin, spi_config[bus].af);
     gpio_init_af(spi_config[bus].miso_pin, spi_config[bus].af);
     gpio_init_af(spi_config[bus].sclk_pin, spi_config[bus].af);
@@ -126,6 +116,23 @@ int spi_init_cs(spi_t bus, spi_cs_t cs)
     return SPI_OK;
 }
 
+#ifdef MODULE_PERIPH_SPI_GPIO_MODE
+int spi_init_gpio_mode(spi_t bus, spi_gpio_mode_t mode)
+{
+    int ret = 0;
+
+#ifdef CPU_FAM_STM32F1
+    /* This has no effect on STM32F1 */
+    return ret;
+#else
+    ret += gpio_init(spi_config[bus].mosi_pin, mode.mosi);
+    ret += gpio_init(spi_config[bus].miso_pin, mode.miso);
+    ret += gpio_init(spi_config[bus].sclk_pin, mode.sclk);
+    return ret;
+#endif
+}
+#endif
+
 int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
 {
     /* lock bus */