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samd21:setup all clock generators in clock.c
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Dan Evans committed Aug 29, 2017
1 parent 09f654e commit 82d692b
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Showing 10 changed files with 417 additions and 320 deletions.
30 changes: 20 additions & 10 deletions boards/arduino-mkr-common/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,14 +33,15 @@ extern "C" {
/**
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
* There are three choices for selection of CORECLOCK:
*
* - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
* stable clock with less jitter. This is why this option is default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
Expand All @@ -61,19 +62,28 @@ extern "C" {
*
* @{
*/
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_XOSC32_DFLL (0)
#define CLOCK_USE_8MHZ_DEFAULT (0)

#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000UL)
#define CLOCK_XOSC32K (32768UL)
#define GEN2_XOSC32 (1)
#elif CLOCK_USE_8MHZ_DEFAULT
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#else
#error Need to select a core clock
#endif
/** @} */

Expand Down Expand Up @@ -230,7 +240,7 @@ static const spi_conf_t spi_config[] = {
#define I2C_0_SCL GPIO_PIN(PA, 9) /* SERCOM0-SCL, on-board pull-up */
#define I2C_0_MUX GPIO_MUX_C
/** @} */

/**
* @name RTC configuration
* @{
Expand All @@ -250,7 +260,7 @@ static const spi_conf_t spi_config[] = {
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
#define XOSC32_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */

#ifdef __cplusplus
Expand Down
32 changes: 21 additions & 11 deletions boards/arduino-zero/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,16 +33,17 @@ extern "C" {
#endif

/**
* @brief External oscillator and clock configuration
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
* There are three choices for selection of CORECLOCK:
*
* - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
* stable clock with less jitter. This is why this option is default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
Expand All @@ -63,19 +64,28 @@ extern "C" {
*
* @{
*/
#define CLOCK_USE_PLL (1)

#define CLOCK_USE_PLL (1)
#define CLOCK_USE_XOSC32_DFLL (0)
#define CLOCK_USE_8MHZ_DEFAULT (0)

#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000UL)
#define CLOCK_XOSC32K (32768UL)
#define GEN2_XOSC32 (1)
#elif CLOCK_USE_8MHZ_DEFAULT
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#else
#error Need to select a core clock
#endif
/** @} */

Expand Down Expand Up @@ -233,7 +243,7 @@ static const spi_conf_t spi_config[] = {
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
#define XOSC32_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */

#ifdef __cplusplus
Expand Down
15 changes: 9 additions & 6 deletions boards/samd21-xpro/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,9 @@ extern "C" {
*
* @{
*/
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_XOSC32_DFLL (0)
#define CLOCK_USE_8MHZ_DEFAULT (0)

#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
Expand All @@ -73,15 +75,16 @@ extern "C" {
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000U)
#define CLOCK_CORECLOCK (48000000UL)
#define CLOCK_XOSC32K (32768UL)
#define CLOCK_8MHZ (1)
#define GEN2_ULP32K (1)
#else
#define GEN2_XOSC32 (1)
#elif CLOCK_USE_8MHZ_DEFAULT
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#else
#error Need to select a core clock
#endif
/** @} */

Expand Down Expand Up @@ -271,7 +274,7 @@ static const spi_conf_t spi_config[] = {
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
#define XOSC32_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */

/**
Expand Down
17 changes: 10 additions & 7 deletions boards/samr21-xpro/include/periph_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,9 @@ extern "C" {
*
* @{
*/
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_XOSC32_DFLL (0)
#define CLOCK_USE_8MHZ_DEFAULT (0)

#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
Expand All @@ -72,16 +74,17 @@ extern "C" {
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000U)
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000UL)
#define CLOCK_XOSC32K (32768UL)
#define CLOCK_8MHZ (1)
#define GEN2_ULP32K (1)
#else
#define GEN2_XOSC32 (1)
#elif CLOCK_USE_8MHZ_DEFAULT
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#else
#error Need to select a core clock
#endif
/** @} */

Expand Down Expand Up @@ -244,7 +247,7 @@ static const spi_conf_t spi_config[] = {
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
#define XOSC32_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */

/**
Expand Down
30 changes: 20 additions & 10 deletions boards/sodaq-autonomo/include/periph_conf.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,16 +29,17 @@ extern "C" {
#endif

/**
* @name External oscillator and clock configuration
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
* There are three choices for selection of CORECLOCK:
*
* - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
* stable clock with less jitter. This is why this option is default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
Expand All @@ -59,19 +60,28 @@ extern "C" {
*
* @{
*/
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_PLL (1)
#define CLOCK_USE_XOSC32_DFLL (0)
#define CLOCK_USE_8MHZ_DEFAULT (0)

#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#elif CLOCK_USE_XOSC32_DFLL
/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
#define CLOCK_CORECLOCK (48000000UL)
#define CLOCK_XOSC32K (32768UL)
#define GEN2_XOSC32 (1)
#elif CLOCK_USE_8MHZ_DEFAULT
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#else
#error Need to select a core clock
#endif
/** @} */

Expand Down Expand Up @@ -242,7 +252,7 @@ static const spi_conf_t spi_config[] = {
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
#define XOSC32_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */

#ifdef __cplusplus
Expand Down
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