Merge #19843

19843: cpu/stm32/periph: add FMC/FSMC support for STM32 r=aabadie a=gschorcht

### Contribution description

The PR provides a driver for STM32 FMC/FSMC peripherals. It supports:
- NOR Flashes,
- PSRAMs/SRAMs,
- SDRAMs, and
- Display Controllers with MCU 8-/16-bit parallel interface.

NAND Flashes are not yet supported.

To use the FMC/FSMC, the `periph_fmc` module has to be enabled. To keep required data structures and resulting code as small as possible, a couple of pseudomodules are defined that have to be used in addition to the `periph_fmc` module to enable supported features. These are:
 
| Module | Feature |
|:-----------------------|:----------------------------------------|
| `periph_fmc_nor_sram`  | enable NOR Flash and PSRAM/SRAM support |
| `periph_fmc_sdram`     | enable SDRAM support                    |
| `periph_fmc_16bit`     | enable 16-bit support                   |
| `periph_fmc_32bit`     | enable 32-bit support                   |

The board has then to define
- the corresponding features according to the connected external device,
- the peripheral configuration of the FMC/FSMC of type `fmc_conf_t,`
- the configuration of the FMC banks which describe the connected external devices.

The PR includes the support for
- `stm32f429i-disc1` with 8 MByte SDRAM
- `stm32f746g-disco` with 16 MByte SDRAM
- `stm32l496g-disco` with 1 MByte SRAM
- `stm32f723e-disco` with 1 MByte SRAM.

To use the RAM connected to the FMC as heap, the board defines `FMC_RAM_ADDR` and ` FMC_RAM_LEN`. For that purpose:
- the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set,
- a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols
- a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and
- the number of heaps is set to 4 to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present.

Once the `drivers/st77xx` and `drivers/lcd` changes are merged, the display for boards like 
the `stm32l496g-disco` and `stm32f723e-disco` can also use the FMC peripheral.

~**NOTE**: The PR includes the fix in PR #19842 for now (commit 560fea1).~

### Testing procedure

1. Use one of the boards above and flash `tests/driver/stm32_fmc`, for example:
   ```
   BOARD=stm32f429i-disc1 make -j8 -C tests/drivers/stm32_fmc flash test
   ```
   The test should succeed.
   
   **NOTE**: There is still a problem with `stm32f746g-disco`. It crashes with a hard-fault on accessing the upper 8 MByte of the 16 MByte.
   
2. Use the board above and flash `tests/sys/malloc`, for example:
   ```
   USEMODULE=periph_fmc CFLAGS='-DCHUNK_SIZE=4096 -DDEBUG_ASSERT_VERBOSE' \
   BOARD=stm32f429i-disc1 make -j8 -C tests/sys/malloc
   ```
   The FMC RAM should be used for `malloc`. On `stm32f746g-disco` for example
   ```
   ...
   Allocated 4096 Bytes at 0x2002d7c8, total 184672
   Allocated 4096 Bytes at 0x2002e7e0, total 188776
   Allocated 4096 Bytes at 0xd0000008, total 192880
   Allocated 4096 Bytes at 0xd0001010, total 196984
   Allocated 4096 Bytes at 0xd0002018, total 201088
   ...
   Allocated 4096 Bytes at 0xd07fd6d0, total 8544520
   Allocated 4096 Bytes at 0xd07fe6e8, total 8548624
   Allocations count: 2083
   ```

### Issues/PRs references

~Depends on PR #19842~

Co-authored-by: Gunar Schorcht <gunar@schorcht.net>

boards/stm32f429i-disc1/Kconfig

@@ -15,6 +15,9 @@ config BOARD_STM32F429I_DISC1
 
     # Put defined MCU peripherals here (in alphabetical order)
     select HAS_PERIPH_DMA
+    select HAS_PERIPH_FMC
+    select HAS_PERIPH_FMC_SDRAM
+    select HAS_PERIPH_FMC_16BIT
     select HAS_PERIPH_I2C
     select HAS_PERIPH_SPI
     select HAS_PERIPH_TIMER

boards/stm32f429i-disc1/Makefile.dep

@@ -2,6 +2,10 @@ ifneq (,$(filter periph_usbdev,$(USEMODULE)))
   USEMODULE += periph_usbdev_hs
 endif
 
+ifneq (,$(filter periph_fmc,$(USEMODULE)))
+  FEATURES_REQUIRED += periph_fmc_16bit
+endif
+
 ifneq (,$(filter saul_default,$(USEMODULE)))
   USEMODULE += saul_gpio
   USEMODULE += l3gxxxx

boards/stm32f429i-disc1/Makefile.features

@@ -3,6 +3,9 @@ CPU_MODEL = stm32f429zi
 
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_dma
+FEATURES_PROVIDED += periph_fmc
+FEATURES_PROVIDED += periph_fmc_16bit
+FEATURES_PROVIDED += periph_fmc_sdram
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer

boards/stm32f429i-disc1/Makefile.include

@@ -8,3 +8,6 @@ OPENOCD_DEBUG_ADAPTER ?= stlink
 
 # openocd programmer is supported
 PROGRAMMERS_SUPPORTED += openocd
+
+FMC_RAM_ADDR=0xd0000000
+FMC_RAM_LEN=8192K

boards/stm32f429i-disc1/include/periph_conf.h

@@ -132,6 +132,111 @@ static const i2c_conf_t i2c_config[] = {
 #define I2C_NUMOF           ARRAY_SIZE(i2c_config)
 /** @} */
 
+/**
+ * @name    FMC configuration
+ * @{
+ */
+/**
+ * @brief   FMC controller configuration
+ */
+static const fmc_conf_t fmc_config = {
+    .bus = AHB3,
+    .rcc_mask = RCC_AHB3ENR_FMCEN,
+#if MODULE_PERIPH_FMC_SDRAM
+    .ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, },     /* FMC_BA0 signal */
+    .ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, },     /* FMC_BA1 signal */
+    .sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, },   /* FMC_SDCLK signal */
+    .sdnwe_pin = { .pin = GPIO_PIN(PORT_C, 0), .af = GPIO_AF12, },   /* FMC_SDNWE signal */
+    .sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
+    .sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
+    .sdcke1_pin = { .pin = GPIO_PIN(PORT_B, 5), .af = GPIO_AF12, },  /* FMC_SDCKE1 signal */
+    .sdne1_pin = { .pin = GPIO_PIN(PORT_B, 6), .af = GPIO_AF12, },   /* FMC_SDNE1 signal */
+    .addr = {
+        { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, },  /* FMC_A0 signal */
+        { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, },  /* FMC_A1 signal */
+        { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, },  /* FMC_A2 signal */
+        { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, },  /* FMC_A3 signal */
+        { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, },  /* FMC_A4 signal */
+        { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, },  /* FMC_A5 signal */
+        { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
+        { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
+        { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
+        { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
+        { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, },  /* FMC_A10 signal */
+        { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, },  /* FMC_A11 signal */
+    },
+#endif
+    .data = {
+        { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
+        { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
+        { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, },  /* FMC_D2 signal */
+        { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, },  /* FMC_D3 signal */
+        { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, },  /* FMC_D4 signal */
+        { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, },  /* FMC_D5 signal */
+        { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, },  /* FMC_D6 signal */
+        { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
+#if MODULE_PERIPH_FMC_16BIT
+        { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
+        { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
+        { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
+        { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
+        { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
+        { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, },  /* FMC_D13 signal */
+        { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, },  /* FMC_D14 signal */
+        { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
+#endif
+    },
+    .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, },    /* FMC_NBL0 signal (LB) */
+    .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, },    /* FMC_NBL1 signal (UB) */
+};
+
+/**
+ * @brief   FMC Bank configuration
+ *
+ * The board has a SDRAM IS42S16400J-7TL with 64 MBit on-board.
+ * It is organized in 4 banks of 1M x 16 bits each and connected to bank 6
+ * at address 0xd0000000.
+ */
+static const fmc_bank_conf_t fmc_bank_config[] = {
+    /* bank 6 is used for SDRAM */
+    {
+        .bank = FMC_BANK_6,
+        .mem_type = FMC_SDRAM,
+        .data_width = FMC_BUS_WIDTH_16BIT,
+        .address = 0xd0000000,               /* Bank 6 is mapped to 0xd0000000 */
+        .size = MiB(8),                      /* Size in Mbyte, 4M x 16 bit */
+        .sdram = {
+            .clk_period = 2,                 /* SDCLK = 2 x HCLK */
+            .row_bits = 12,                  /* A11..A0 used for row address */
+            .col_bits = 8,                   /* A8..A0 used for column address */
+            .cas_latency = 3,                /* CAS latency is 3 clock cycles */
+            .read_delay = 0,                 /* No read delay after CAS */
+            .burst_read = false,             /* Burst read mode disabled */
+            .burst_write = false,            /* Burst write mode disabled */
+            .burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 if enabled */
+            .burst_interleaved = false,      /* Burst mode interleaved */
+            .write_protect = false,          /* No write protection */
+            .four_banks = true,              /* SDRAM has four internal banks */
+            .timing = {                      /* SDRAM Timing parameters */
+                .row_to_col_delay = 2,       /* Row to column delay (2 clock cycles) */
+                .row_precharge = 2,          /* Row precharge delay (2 clock cycles) */
+                .recovery_delay = 2,         /* Recovery delay is (2 clock cycles) */
+                .row_cylce = 7,              /* Row cycle delay is (7 clock cycles) */
+                .self_refresh = 4,           /* Self refresh time is (4 clock cycles) */
+                .exit_self_refresh = 7,      /* Exit self-refresh delay (7 clock cycles) */
+                .load_mode_register = 2,     /* Load Mode Register to Activate delay */
+                .refresh_period = 64,        /* Refresh period in ms */
+            },
+        },
+    },
+};
+
+/**
+ * @brief   Number of configured FMC banks
+ */
+#define FMC_BANK_NUMOF  ARRAY_SIZE(fmc_bank_config)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/stm32f723e-disco/Kconfig

@@ -14,6 +14,9 @@ config BOARD_STM32F723E_DISCO
     select CPU_MODEL_STM32F723IE
 
     # Put defined MCU peripherals here (in alphabetical order)
+    select HAS_PERIPH_FMC
+    select HAS_PERIPH_FMC_16BIT
+    select HAS_PERIPH_FMC_NOR_SRAM
     select HAS_PERIPH_I2C
     select HAS_PERIPH_RTC
     select HAS_PERIPH_RTT

boards/stm32f723e-disco/Makefile.dep

@@ -10,6 +10,10 @@ ifneq (,$(filter touch_dev,$(USEMODULE)))
   USEMODULE += ft5x06
 endif
 
+ifneq (,$(filter periph_fmc,$(USEMODULE)))
+  FEATURES_REQUIRED += periph_fmc_16bit
+endif
+
 ifneq (,$(filter periph_spi,$(USEMODULE)))
   # The LED pin is also used for SPI
   DISABLE_MODULE += periph_init_led0

boards/stm32f723e-disco/Makefile.features

@@ -3,6 +3,9 @@ CPU = stm32
 CPU_MODEL = stm32f723ie
 
 # Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_fmc
+FEATURES_PROVIDED += periph_fmc_16bit
+FEATURES_PROVIDED += periph_fmc_nor_sram
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_rtc
 FEATURES_PROVIDED += periph_rtt

boards/stm32f723e-disco/Makefile.include

@@ -13,3 +13,8 @@ PROGRAMMERS_SUPPORTED += openocd
 # The board can become un-flashable after some execution or after being plugged,
 # use connect_assert_srst to always be able to flash or reset the board.
 OPENOCD_RESET_USE_CONNECT_ASSERT_SRST ?= 1
+
+# Since only 18 of the 19 address lines are connected, only 512 kByte of the
+# 1 MByte PSRAM can be used.
+FMC_RAM_ADDR=0x60000000
+FMC_RAM_LEN=512K

boards/stm32f723e-disco/include/periph_conf.h

@@ -232,6 +232,107 @@ static const spi_conf_t spi_config[] = {
 #define SPI_NUMOF           ARRAY_SIZE(spi_config)
 /** @} */
 
+/**
+ * @name    FMC configuration
+ * @{
+ */
+
+/**
+ * @brief   FMC controller configuration
+ */
+static const fmc_conf_t fmc_config = {
+    .bus = AHB3,
+    .rcc_mask = RCC_AHB3ENR_FMCEN,
+#if MODULE_PERIPH_FMC_NOR_SRAM
+    .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* PSRAM_NE1 signal, subbank 1 */
+    .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 2 */
+    .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* LCD_PSRAM_NOE */
+    .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* LCD_PSRAM_NWE signal */
+    .addr = {
+        { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, },  /* PSRAM_A0 / LCD_RS signal */
+        { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, },  /* PSRAM_A1 signal */
+        { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, },  /* PSRAM_A2 signal */
+        { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, },  /* PSRAM_A3 signal */
+        { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, },  /* PSRAM_A4 signal */
+        { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, },  /* PSRAM_A5 signal */
+        { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
+        { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
+        { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
+        { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
+        { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, },  /* PSRAM_A10 signal */
+        { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, },  /* PSRAM_A11 signal */
+        { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, },  /* PSRAM_A12 signal */
+        { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, },  /* PSRAM_A13 signal */
+        { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, },  /* PSRAM_A14 signal */
+        { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, },  /* PSRAM_A15 signal */
+        { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
+        { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
+    },
+#endif
+    .data = {
+        { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D0 signal */
+        { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D1 signal */
+        { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, },  /* LCD_PSRAM_D2 signal */
+        { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, },  /* LCD_PSRAM_D3 signal */
+        { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, },  /* LCD_PSRAM_D4 signal */
+        { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, },  /* LCD_PSRAM_D5 signal */
+        { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, },  /* LCD_PSRAM_D6 signal */
+        { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D7 signal */
+#if MODULE_PERIPH_FMC_16BIT
+        { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* LCD_PSRAM_D8 signal */
+        { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* LCD_PSRAM_D9 signal */
+        { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* LCD_PSRAM_D10 signal */
+        { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D11 signal */
+        { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D12 signal */
+        { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, },  /* LCD_PSRAM_D13 signal */
+        { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, },  /* LCD_PSRAM_D14 signal */
+        { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D15 signal */
+#endif
+    },
+    .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
+    .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
+};
+
+/**
+ * @brief   FMC Bank configuration
+ *
+ * The board has a PSRAM IS66WV51216EBLL-55BLI with  MBit on-board.
+ * It is organized in 512K x 16 bits and connected to bank 1, subbank 1
+ * at address 0x60000000.
+ *
+ * @note A18 of the PSRAM is not used. Therefore, only 256K x 16 bits
+ *       (512 kByte) of the 1 MByte PSRAM can be used.
+ *
+ * The LCD display of the board is connected to bank 1, subbank2
+ * at address 0x64000000.
+ */
+static const fmc_bank_conf_t fmc_bank_config[] = {
+    /* bank 1, subbank 1 is used for PSRAM with asynchronuous
+     * access in Mode 1, i.e. write timings are not used */
+    {
+        .bank = FMC_BANK_1,
+        .mem_type = FMC_SRAM,
+        .data_width = FMC_BUS_WIDTH_16BIT,
+        .address = 0x60000000,  /* Bank 1, subbank 1 is mapped to 0x60000000 */
+        .size = KiB(512),       /* Size in byte, 256K x 16 bit */
+        .nor_sram = {
+            .sub_bank = 1,
+            .ext_mode = false,                      /* Mode 1 used, no separate w_timing */
+                                                    /* timings for IS66WV51216EBLL-55BLI
+                                                       @216 MHz AHB clock */
+            .r_timing = {  .addr_setup = 13,        /* t_AA = max 60 ns (13 HCLKs a 4.63 ns) */
+                           .data_setup = 6,         /* t_SD = min 25 ns (6 HCLKs a 4.63 ns) */
+                           .bus_turnaround = 3, },  /* 3 HCLKs a 4.63 ns */
+        },
+    },
+};
+
+/**
+ * @brief   Number of configured FMC banks
+ */
+#define FMC_BANK_NUMOF  ARRAY_SIZE(fmc_bank_config)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

boards/stm32f746g-disco/Kconfig

@@ -15,6 +15,9 @@ config BOARD_STM32F746G_DISCO
     # Put defined MCU peripherals here (in alphabetical order)
     select HAS_PERIPH_DMA
     select HAS_PERIPH_ETH
+    select HAS_PERIPH_FMC
+    select HAS_PERIPH_FMC_SDRAM
+    select HAS_PERIPH_FMC_16BIT
     select HAS_PERIPH_I2C
     select HAS_PERIPH_LTDC
     select HAS_PERIPH_RTC

boards/stm32f746g-disco/Makefile.dep

@@ -13,3 +13,7 @@ endif
 ifneq (,$(filter touch_dev,$(USEMODULE)))
   USEMODULE += ft5x06
 endif
+
+ifneq (,$(filter periph_fmc,$(USEMODULE)))
+  FEATURES_REQUIRED += periph_fmc_16bit
+endif

boards/stm32f746g-disco/Makefile.include

@@ -13,3 +13,6 @@ PROGRAMMERS_SUPPORTED += openocd
 # The board can become un-flashable after some execution,
 # use connect_assert_srst to always be able to flash or reset the board.
 OPENOCD_RESET_USE_CONNECT_ASSERT_SRST ?= 1
+
+FMC_RAM_ADDR=0xc0000000
+FMC_RAM_LEN=8192K

boards/stm32f746g-disco/features-shared.mk

@@ -1,6 +1,9 @@
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_dma
 FEATURES_PROVIDED += periph_eth
+FEATURES_PROVIDED += periph_fmc
+FEATURES_PROVIDED += periph_fmc_16bit
+FEATURES_PROVIDED += periph_fmc_sdram
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_ltdc
 FEATURES_PROVIDED += periph_rtc