boards/nrf5340dk-app: add SPI flash configuration

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>

boards/nrf5340dk-app/Makefile.dep

@@ -0,0 +1,9 @@
+ifneq (,$(filter mtd,$(USEMODULE)))
+  USEMODULE += mtd_spi_nor
+endif
+
+# default to using littlefs2 on the external flash
+ifneq (,$(filter vfs_default,$(USEMODULE)))
+  USEPKG += littlefs2
+  USEMODULE += mtd
+endif

boards/nrf5340dk-app/board.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nrf5340dk-app
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the Nordic nRF5340DK board
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+#include "timex.h"
+#ifdef MODULE_VFS_DEFAULT
+#include "vfs_default.h"
+#endif
+
+#ifdef MODULE_MTD_SPI_NOR
+#include "mtd_spi_nor.h"
+/* MX25R64 */
+static const mtd_spi_nor_params_t _nrf5340_nor_params = {
+    .opcode = &mtd_spi_nor_opcode_default,
+    .wait_chip_erase = 240 * US_PER_SEC,
+    .wait_64k_erase = 800 * US_PER_MS,
+    .wait_sector_erase = 240 * US_PER_MS,
+    .wait_chip_wake_up = 1 * US_PER_MS,
+    .clk  = MHZ(54),
+    .flag = SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_64K,
+    .spi  = SPI_DEV(0),
+    .mode = SPI_MODE_0,
+    .cs   = BOARD_QSPI_PIN_CS,
+    .wp   = BOARD_QSPI_PIN_WP,
+    .hold = BOARD_QSPI_PIN_HOLD,
+};
+
+static mtd_spi_nor_t nrf5340_nor_dev = {
+    .base = {
+        .driver = &mtd_spi_nor_driver,
+        .page_size = 256,
+        .pages_per_sector = 16,
+    },
+    .params = &_nrf5340_nor_params,
+};
+mtd_dev_t *mtd0 = (mtd_dev_t *)&nrf5340_nor_dev;
+
+#ifdef MODULE_VFS_DEFAULT
+VFS_AUTO_MOUNT(littlefs2, VFS_MTD(nrf5340_nor_dev), VFS_DEFAULT_NVM(0), 0);
+#endif
+#endif /* MODULE_MTD_SPI_NOR */

boards/nrf5340dk-app/include/board.h

@@ -20,6 +20,7 @@
 #define BOARD_H
 
 #include "cpu.h"
+#include "mtd.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -95,6 +96,20 @@ extern "C" {
 #define BTN3_MODE           GPIO_IN_PU       /**< BTN3 default mode */
 /** @} */
 
+
+/**
+ * @name MTD configuration
+ * @{
+ */
+extern mtd_dev_t *mtd0;
+#define MTD_0       mtd0
+#define MTD_NUMOF   1
+
+#define BOARD_QSPI_PIN_CS       GPIO_PIN(0, 18)
+#define BOARD_QSPI_PIN_WP       GPIO_PIN(0, 15)
+#define BOARD_QSPI_PIN_HOLD     GPIO_PIN(0, 16)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif