cpu/stm32: optimize stop mode for stm32f*

[fjmolinas]

Contribution description

This PR is based on previous work in #11359, where STM32L1 has been cut from the PR.

On start-up it configures all GPIO's as AIN. On other boards of the STM32 family (L0 & L4) this is done by default. There for this is only done for STM32F0-7~.

As stated in this AN, doing this saves the consumption of the input Schmitt trigger. The only case where this shouldn't be done is when the pin is connected to an external driver that has a pull-up or pull-down setting, this should be handled by pertinent drivers.

Testing procedure

Supply voltage for all the below measurement was 3.3V. Al pin headers where disconnected where disconnected, supply was measured directly threw the IDD pin either with a multi meter or NUCLEO-LPM01A power measurement extension.

As of know when entering STOP mode consumption on stm32f7 is around 1.24mA, with this PR it drops to 350uA (270uA typ f746zg). To test run:

make BOARD=nucleo-f746zg -C tests/periph_pm/ flash

As of know when entering STOP mode consumption on stm32f4 is around 500uA, with this PR it drops to 120uA (datasheet 120uA typ for f446re). To test run:

make BOARD=nucleo-f446re -C tests/periph_pm/ flash

As of know when entering STOP mode consumption on stm32f3 is around 1mA, with this PR it drops to 15.3uA (datasheet 7.4uA typ for f303re). To test run:

make BOARD=nucleo-f303re -C tests/periph_pm/ flash

As of know when entering STOP mode consumption on stm32f2 is around 1.27mA, with this PR it drops to 200uA (datasheet 200uA typ for f207zg). To test run:

make BOARD=nucleo-f207zg -C tests/periph_pm/ flash

As of know when entering STOP mode consumption on stm32f1 is around 100uA, with this PR it drops to 11uA (13.5uA typ f103rb). Tested on nucleo-f103rb:

make BOARD=nucleo-f103rb -C tests/periph_pm/ flash

As of know when entering STOP mode consumption on stm32f0 is around 507uA, with this PR it drops to 10.7uA (3.5uA typ f072rb). To test run:

make BOARD=nucleo-f072rb -C tests/periph_pm/ flash

NOTE: on nucleo boards if power is measured directly after programming there will be around 200uA of current consumption coming from the stlink. The stlink must start without being connected to the board or power the board externally.

Issues/PRs references

Based on work from #8403 & #10052. Taken from #11359.

[aabadie]

I tested this PR on all related platforms: F0, F1, F2, F3, F4 and F7. I confirm the power consumption measures reported.

[aabadie]

Codewise the changes looks good but I'd like to have someone else's opinion on that. Maybe @kaspar030 ?

[fjmolinas]

@aabadie I wanted to perform a dist/tools/compile_and_test_for_board/compile_and_test_for_board.py for all tests to verify that this would not affect any test. I tested on nucleo-f303ze with no issues, so I don't have any reason for staling anymore.

[aabadie]

Murdock raised an issue with the current design: adding gpio_pm_init_ain in periph/gpio.c introduces an implicit dependency on periph_gpio feature.

I think this function should be moved to cpu_init and be static inline. Then there's no need to provide a new function in the public API.
Does it make sense to you @fjmolinas ?

[fjmolinas]

I think this function should be moved to cpu_init and be static inline. Then there's no need to provide a new function in the public API.

Its going to bloat cpu_init code. Anyway I did as you suggested, I'll need to rebase and re-write the commit history and messaged to properly reflect this.

[aabadie]

Anyway I did as you suggested, I'll need to rebase and re-write the commit history and messaged to properly reflect this.

Thanks, I'll do another round of review ASAP.

[aabadie]

This can be made static inline

[kaspar030]

only static should suffice

[kaspar030]

IMO readablility can be improved by a) seperating the two switch cases, and b) turning the "DISABLE_JTAG" test into a C-level if statement:

https://gist.github.com/4fd5be0cfdaeede87c3b87b7d732887f

[fjmolinas]

IMO readablility can be improved by a) seperating the two switch cases, and b) turning the "DISABLE_JTAG" test into a C-level if statement:

Thanks for the suggestion, I was thinking the same thing. I applied the diff.

Also I removed the break a because I realized for some cpu's GPIO's are not in a sequential order so I need to check all ports and not break immediately. e.g. "stm32f410"

#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)

[fjmolinas]

@aabadie are you ok with the changes? Should I squash?

[aabadie]

ACK, please squash!

[aabadie]

Let's go with this one :)