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cpu/atmega_common: implement periph/gpio_ll{,_irq} #17982
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I ran the test on microduino-corerf
with
PORT_IN ?= 4 # E
PORT_OUT ?= 3 # D
PIN_IN_0 ?= 4
PIN_IN_1 ?= 5
PIN_OUT_0 ?= 2
PIN_OUT_1 ?= 3
2022-05-02 02:26:35,353 # main(): This is RIOT! (Version: 2022.07-devel-163-g113f4-HEAD)
2022-05-02 02:26:35,356 # Test / Hardware Deatils:
2022-05-02 02:26:35,358 # ========================
2022-05-02 02:26:35,359 # Cabling:
2022-05-02 02:26:35,361 # P4.4 (PE4) -- P3.2 (PD2)
2022-05-02 02:26:35,363 # P4.5 (PE5) -- P3.3 (PD3)
2022-05-02 02:26:35,367 # Number of pull resistor values supported: 1
2022-05-02 02:26:35,371 # Number of drive strengths supported: 1
2022-05-02 02:26:35,374 # Number of slew rates supported: 1
2022-05-02 02:26:35,376 # Valid GPIO ports:
2022-05-02 02:26:35,377 # - PORT 0 (PORT A)
2022-05-02 02:26:35,379 # - PORT 1 (PORT B)
2022-05-02 02:26:35,380 # - PORT 2 (PORT C)
2022-05-02 02:26:35,382 # - PORT 3 (PORT D)
2022-05-02 02:26:35,384 # - PORT 4 (PORT E)
2022-05-02 02:26:35,385 # - PORT 5 (PORT F)
2022-05-02 02:26:35,387 # - PORT 6 (PORT G)
2022-05-02 02:26:35,387 #
2022-05-02 02:26:35,390 # Testing gpio_port_pack_addr()
2022-05-02 02:26:35,392 # =============================
2022-05-02 02:26:35,393 #
2022-05-02 02:26:35,393 # All OK
2022-05-02 02:26:35,393 #
2022-05-02 02:26:35,395 # Testing gpip_ng_init()
2022-05-02 02:26:35,397 # ======================
2022-05-02 02:26:35,398 #
2022-05-02 02:26:35,403 # Testing is_gpio_port_num_valid() is true for PORT_OUT and PORT_IN:
2022-05-02 02:26:35,404 #
2022-05-02 02:26:35,407 # Testing input configurations for PIN_IN_0:
2022-05-02 02:26:35,411 # Support for input with pull up: yes
2022-05-02 02:26:35,415 # state: in, pull: up, schmitt trigger: on, value: on
2022-05-02 02:26:35,419 # Support for input with pull down: no
2022-05-02 02:26:35,423 # Support for input with pull to bus level: no
2022-05-02 02:26:35,427 # Support for floating input (no pull resistors): yes
2022-05-02 02:26:35,432 # state: in, pull: none, schmitt trigger: on, value: on
2022-05-02 02:26:35,433 #
2022-05-02 02:26:35,436 # Testing output configurations for PIN_OUT_0:
2022-05-02 02:26:35,442 # Support for output (push-pull) with initial value of LOW: yes
2022-05-02 02:26:35,444 # state: out-pp, value: off
2022-05-02 02:26:35,448 # Output is indeed LOW: yes
2022-05-02 02:26:35,450 # state: out-pp, value: on
2022-05-02 02:26:35,454 # Output can be pushed HIGH: yes
2022-05-02 02:26:35,460 # Support for output (push-pull) with initial value of HIGH: yes
2022-05-02 02:26:35,462 # state: out-pp, value: on
2022-05-02 02:26:35,465 # Output is indeed HIGH: yes
2022-05-02 02:26:35,472 # Support for output (open drain with pull up) with initial value of LOW: no
2022-05-02 02:26:35,479 # Support for output (open drain with pull up) with initial value of HIGH: no
2022-05-02 02:26:35,484 # Support for output (open drain) with initial value of LOW: no
2022-05-02 02:26:35,490 # Support for output (open drain) with initial value of HIGH: no
2022-05-02 02:26:35,496 # Support for output (open source) with initial value of LOW: no
2022-05-02 02:26:35,502 # Support for output (open drain) with initial value of HIGH: no
2022-05-02 02:26:35,508 # Support for output (open drain with pull up) with initial value of HIGH: no
2022-05-02 02:26:35,515 # Support for output (open drain with pull up) with initial value of LOW: no
2022-05-02 02:26:35,518 # Support for disconnecting GPIO: yes
2022-05-02 02:26:35,525 # WARN: Cannot enable pull down of PIN_IN_0 to verify correct disabled behavior
2022-05-02 02:26:35,530 # Output can indeed be pulled HIGH: yes
2022-05-02 02:26:35,530 #
2022-05-02 02:26:35,533 # Testing Reading/Writing GPIO Ports
2022-05-02 02:26:35,536 # ==================================
2022-05-02 02:26:35,536 #
2022-05-02 02:26:35,540 # testing initial value of 0 after init
2022-05-02 02:26:35,541 # ...OK
2022-05-02 02:26:35,546 # testing setting both outputs_optional simultaneously
2022-05-02 02:26:35,548 # ...OK
2022-05-02 02:26:35,553 # testing clearing both outputs_optional simultaneously
2022-05-02 02:26:35,554 # ...OK
2022-05-02 02:26:35,558 # testing toggling first output (0 --> 1)
2022-05-02 02:26:35,559 # ...OK
2022-05-02 02:26:35,563 # testing toggling first output (1 --> 0)
2022-05-02 02:26:35,565 # ...OK
2022-05-02 02:26:35,568 # testing toggling second output (0 --> 1)
2022-05-02 02:26:35,570 # ...OK
2022-05-02 02:26:35,574 # testing toggling second output (1 --> 0)
2022-05-02 02:26:35,575 # ...OK
2022-05-02 02:26:35,581 # testing setting first output and clearing second with write
2022-05-02 02:26:35,582 # ...OK
2022-05-02 02:26:35,588 # testing setting second output and clearing first with write
2022-05-02 02:26:35,588 # ...OK
2022-05-02 02:26:35,593 # All input/output operations worked as expected
2022-05-02 02:26:35,593 #
2022-05-02 02:26:35,595 # Testing External IRQs
2022-05-02 02:26:35,597 # =====================
2022-05-02 02:26:35,597 #
2022-05-02 02:26:35,599 # Testing rising edge on PIN_IN_0
2022-05-02 02:26:35,604 # ... OK
2022-05-02 02:26:35,607 # Testing falling edge on PIN_IN_0
2022-05-02 02:26:35,611 # ... OK
2022-05-02 02:26:35,614 # Testing both edges on PIN_IN_0
2022-05-02 02:26:35,618 # ... OK
2022-05-02 02:26:35,623 # Testing masking of IRQs (still both edges on PIN_IN_0)
2022-05-02 02:26:35,630 # ... OK
2022-05-02 02:26:35,637 # Testing level-triggered on LOW on PIN_IN_0 (when input is HIGH when setting up IRQ)
2022-05-02 02:26:35,640 # ... OK
2022-05-02 02:26:35,648 # Testing level-triggered on LOW on PIN_IN_0 (when input is LOW when setting up IRQ)
2022-05-02 02:26:35,650 # ... OK
2022-05-02 02:26:35,650 #
2022-05-02 02:26:35,650 #
2022-05-02 02:26:35,651 # TEST SUCCEEDED
2022-05-02 02:26:35,658 # { "threads": [{ "name": "idle", "stack_size": 128, "stack_used": 108 }]}
2022-05-02 02:26:35,664 # { "threads": [{ "name": "main", "stack_size": 640, "stack_used": 152 }]}
Note that on ATmega the pins for external interrupts are fixed and there are ~3 pins suitable. I haven't checked, but it might be that you have selected pins that just are not suitable for external interrupts. |
The test did work, I indeed had selected a wrong pin initially. |
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Please squash!
Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
Contribution description
Implements
gpio_ll
andgpio_ll_irq
for AVR ATmega MCUs.Testing procedure
Tested successfully for Arduino MEGA2560 and a custom downstream ATmega1284P based board.
Issues/PRs references
Depends on and includes: #16787