cpu/{esp8266,esp32}: cleanup of SPI Flash configuration

[gschorcht]

Contribution description

This PR fixes some inconsistencies in the definition of the correct SPI flash parameters from the FLASH_* variables. In detail it contains the following changes:

• For ESP32x SoC, esptool.py is has to be called with --flash_mode dio when any Quad SPI mode qout or qio is used to let the first stage bootloader always start in Dual SPI mode. That is, dio has to be set as FLASH_MODE variable in makefile/tools/esptool.py if the FLASH_MODE variable is set to qio or dio.
• FLASH_MODE_* defines are replaced by CONFIG_FLASHMODE_* and CONFIG_ESPTOOLPY_FLASHMODE_* defines to be compatible with ESP-IDF. Furthermore, this will also needed for the migration of defining the flash mode in Kconfig. Defining them CFLAGS in the makefile make them visible in whole make system.
• The default flash mode in bootloader has to be dio instead of dout.
• The default flash configuration defined by the FLASH_* variables has to be exported for ESP32 to be also visible in cpu/esp32/bootloader/Makefile.
• The comments in flash configuration defined by the FLASH_* in cpu/esp8266/Makefile.include have to be removed so that the FLASH_* variables do not contain trailing white spaces.
• Flash mode 'qout' is no longer required for SPI-RAM.

Testing procedure

1. Use a esp32-wroom-32 and compile and flash with following command.

   FLASH_MODE=dout FLASH_FREQ=80m FLASH_SIZE=4 USEMODULE='esp_log_startup' \
   BOARD=esp32-wrover-kit make -j8 -C tests/malloc flash term PORT=/dev/ttyUSB0
   

   The output should be something like the following:

   rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
   configsip: 0, SPIWP:0xee
   clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
   mode:DOUT, clock div:1
   load:0x3fff0030,len:6120
   load:0x40078000,len:13732
   load:0x40080400,len:3492
   entry 0x4008041c
   I (27) boot: ESP-IDF v4.4.1 2nd stage bootloader
   I (27) boot: chip revision: 1
   I (27) boot_comm: chip revision: 1, min. bootloader chip revision: 0
   I (30) boot.esp32: SPI Speed      : 80MHz
   I (33) boot.esp32: SPI Mode       : DOUT
   I (37) boot.esp32: SPI Flash Size : 4MB
   

   That is, DOUT is used for the first stage bootloader and the second stage bootloader as well.

2. Use a esp32-wroom-32 and compile and flash with following command.

   FLASH_MODE=qio FLASH_FREQ=80m FLASH_SIZE=4 USEMODULE='esp_log_startup' \
   BOARD=esp32-wrover-kit make -j8 -C tests/malloc flash term PORT=/dev/ttyUSB0
   

   The output should be something like the following:

   rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
   configsip: 0, SPIWP:0xee
   clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
   mode:DIO, clock div:1
   load:0x3fff0030,len:6436
   load:0x40078000,len:14436
   load:0x40080400,len:4192
   entry 0x4008041c
   I (27) boot: ESP-IDF v4.4.1 2nd stage bootloader
   I (27) boot: chip revision: 1
   I (27) boot_comm: chip revision: 1, min. bootloader chip revision: 0
   I (30) qio_mode: Enabling default flash chip QIO
   I (34) boot.esp32: SPI Speed      : 80MHz
   I (38) boot.esp32: SPI Mode       : QIO
   I (41) boot.esp32: SPI Flash Size : 4MB
   

   That is, DIO is used for the first stage bootloader and QIO for the second stage bootloader.

Issues/PRs references

[gschorcht]

@benpicco I found some inconsistencies in using FLASH_MODE variables that have to be fixed. This PR should be merged before all subsequent PRs for ESP2-C3, ESP2-S3 and ESP32-S2 because it affects all of them.

[miri64]

Requeued in Murdock queue to give 2022.07 release backport #18354 precedence.

[benpicco]

esp8266 also still works

[gschorcht]

@benpicco Thanks for reviewing and merging.