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cpu/esp32: define FLASHFILE_POS #19078

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merged 3 commits into from
Jan 2, 2023

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gschorcht
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@gschorcht gschorcht commented Dec 31, 2022

Contribution description

Instead of using a fixed position of the image file in the flash, the variable FLASHFILE_POS is used which allows to override the default position of the image in the flash at 0x10000.

This PR is a prerequisite for the periph_flashpage implementation PR #19079.

Testing procedure

Flashing a ESP32x SoC should work with FLASHFILE_POS=0x20000, for example:

USEMODULE=esp_log_startup FLASHFILE_POS=0x20000 BOARD=esp32-wroom-32 make -j8 -C tests/shell flash

The bootloader output should give 00020000 as offset for the factory partition

I (75) boot: Partition Table:
I (78) boot: ## Label            Usage          Type ST Offset   Length
I (84) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (91) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (97) boot:  2 factory          factory app      00 00 00020000 000199b0
I (104) boot: End of partition table

and

I (125) esp_image: segment 0: paddr=00020020 vaddr=3f400020 size=02140h (  8512) map

during the load of the image.

Issues/PRs references

Prerequisite for PR #19079

Instead of using a fixed position of the image file in the flash, the variable `FLASHFILE_POS` is used which allows to override the default position of the image in the flash at 0x10000.
@github-actions github-actions bot added Area: build system Area: Build system Area: cpu Area: CPU/MCU ports Area: tools Area: Supplementary tools Platform: ESP Platform: This PR/issue effects ESP-based platforms labels Dec 31, 2022
@gschorcht gschorcht added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Dec 31, 2022
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riot-ci commented Dec 31, 2022

Murdock results

✔️ PASSED

a0715b2 cpu/esp32: export FLASH_SIZE to SDK configuration

Success Failures Total Runtime
6765 0 6765 14m:03s

Artifacts

@@ -151,6 +152,19 @@ else ifeq (120m,$(FLASH_FREQ))
CFLAGS += -DCONFIG_ESPTOOLPY_FLASHFREQ_120M
endif

#extend CFLAGS by the corresponding FLASH_SIZE
ifeq (1,$(FLASH_SIZE))
CFLAGS += -DCONFIG_ESPTOOLPY_FLASHSIZE_1MB
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Would it make sense to use

Suggested change
CFLAGS += -DCONFIG_ESPTOOLPY_FLASHSIZE_1MB
CFLAGS += -DCONFIG_ESPTOOLPY_FLASHSIZE_$(FLASH_SIZE)MB

instead or is there only a fixed set of CONFIG_ defines anyway?

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These are the values declared by ESP-IDF's Kconfig.

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bors merge

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bors bot commented Jan 2, 2023

Build succeeded!

And happy new year! 🎉

@bors bors bot merged commit 6b4b754 into RIOT-OS:master Jan 2, 2023
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@benpicco Thanks for reviewing and merging.

bors bot added a commit that referenced this pull request Jan 18, 2023
19079: cpu/esp32: add periph_flashpage support r=kaspar030 a=gschorcht

### Contribution description

This PR provides the `periph_flashpage` support for ESP32x SoCs.

For byte-aligned read access to constant data in the flash, the MMU of all ESP32x SoCs allows to map a certain number of 64 kByte pages of the flash into the data address space of the CPU. This address space is called DROM. Normally the whole DROM address space is assigned to the section `.rodata`. The default flash layout used by all ESP32x SoCs is:
| Address in Flash | Content |
|:-----------------------|:-----------|
| `0x0000` or `0x1000` | bootloader |
| `0x8000` | parition table |
| `0x9000` | `nvs` parition with WiFi data |
| `0xf000`  | `phy_init` partition with RF data |
| `0x10000` | `factory` partition with the app image |

The factory partition consists of a number of 64 kByte pages for the sections `.text`, `.rodata`, `.bss` and others. The `.text` and `rodata` sections are page-aligned and are simply mapped into the instruction address space (IROM) and the data address space (DROM), respectively. All other sections are loaded into RAM.

If the `periph_flashpage` module is used, the `periph_flashpage` driver
- decreases the size of the `.rodata` section in DROM address space by `CONFIG_ESP_FLASHPAGE_CAPACITY`,
- adds a section `.flashpage.writable` of size `CONFIG_ESP_FLASHPAGE_CAPACITY` at the end of DROM address space that is mapped into data address space of the CPU,
- reserves a region of size `CONFIG_ESP_FLASHPAGE_CAPACITY` starting from `0x10000` in front of the image partition `factory` and
- moves the image partition `factory` by  `CONFIG_ESP_FLASHPAGE_CAPACITY` to address `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY`. 

The new flash layout is then:
| Address in Flash | Content |
|:-----------------------|:-----------|
| `0x0000` or `0x1000` | bootloader |
| `0x8000` | parition table |
| `0x9000` | `nvs` parition with WiFi data |
| `0xf000`  | `phy_init` partition with RF data |
| `0x10000` | flashpage region |
| `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY` | `factory` partition with the app image |

This guarantees that the flash pages are not overwritten if a new app image with changed size is flashed. `CONFIG_ESP_FLASHPAGE_CAPACITY` has to be a multiple of 64 kBytes.

~The PR includes PR #19077 and PR #19078 for the moment to be compilable.~

### Testing procedure

The following tests should pass.
```
USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/periph_flashpage flash term
```
```
USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/mtd_flashpage flash term
```

### Issues/PRs references

Depends on PR #19077
Depends on PR #19078 


Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
@gschorcht gschorcht deleted the cpu/esp32/define_flashfile_pos branch January 31, 2023 19:41
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3 participants