cpu/sam0_common/periph_gpio_ll: fix gpio_get_port() and gpio_ll_query_conf() #20999
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It turns out that the legacy GPIO API and GPIO LL may disagree on what the GPIO base address is: GPIO LL will use the IOBUS as base address no matter what, the legacy GPIO API will use the APB as base address unless `periph_gpio_fast_read` is used. If the APIs disagree, we need to do impedance matching.
maribu
added
Type: bug
github-actions
bot
added
Platform: ARM
Wouldn't it be less trouble if GPIO LL behaved the same wrt the use of |
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Well, there is no reason to ever write slow. Only for reading there is a power penalty to pay for fast access. That is why GPIO LL is always using the IOBUS for output (if there is an IOBUS mapping), and APB for read only when The end game is also to get rid of |
For the other MCUs, we take the input register state instead of the output register state when the pin is configured as input. Let's do the same here, as this is a lot more useful and intuitive.
maribu
changed the title
maribu
changed the title
benpicco
approved these changes
Nov 18, 2024
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Backport provided in #21008 |
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Thx :) |
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Contribution description
gpio_get_port()It turns out that the legacy GPIO API and GPIO LL may disagree on what the GPIO base address is: GPIO LL will use the IOBUS as base address no matter what, the legacy GPIO API will use the APB as base address unless
periph_gpio_fast_readis used.If the APIs disagree, we need to do impedance matching.
gpio_ll_query_conf()For the other MCUs, we take the input register state instead of the output register state when the pin is configured as input. Let's do the same here, as this is a lot more useful and intuitive.
Testing procedure
gpio_query_conf(gpio_get_port(GPIO_PIN(PA, 1)), gpio_get_pin_num(GPIO_PIN(PA, 1));should no longer run into a blown assertion.Issues/PRs references
None