kinetis: Implement low power modes

boards/common/frdm/dist/openocd-klx.cfg

@@ -16,7 +16,10 @@ transport select swd
 # Kinetis L series CPUs
 source [find target/klx.cfg]
 
-reset_config srst_only
+# The debug module is stopped in low leakage modes, we use connect_assert_srst
+# to hold the device in reset while connecting with OpenOCD to make sure that we
+# always get a connection even when the application uses low power modes.
+reset_config srst_only connect_assert_srst
 
 $_TARGETNAME configure -event gdb-attach {
   halt

boards/common/frdm/dist/openocd-kx.cfg

@@ -13,7 +13,10 @@
 # Kinetis K series CPUs
 source [find target/kx.cfg]
 
-reset_config srst_only
+# The debug module is stopped in low leakage modes, we use connect_assert_srst
+# to hold the device in reset while connecting with OpenOCD to make sure that we
+# always get a connection even when the application uses low power modes.
+reset_config srst_only connect_assert_srst
 
 $_TARGETNAME configure -event gdb-attach {
   halt

boards/frdm-k22f/include/periph_conf.h

@@ -80,14 +80,15 @@ static const clock_config_t clock_config = {
     },                           \
 }
 #define LPTMR_NUMOF             (1U)
-#define LPTMR_CONFIG {          \
-    {                           \
-        .dev = LPTMR0,          \
-        .irqn = LPTMR0_IRQn,    \
-        .src = 2,               \
-        .base_freq = 32768u,    \
-    },                          \
-}
+#define LPTMR_CONFIG { \
+        { \
+            .dev = LPTMR0, \
+            .base_freq = 32768u, \
+            .llwu = LLWU_WAKEUP_MODULE_LPTMR0, \
+            .src = 2, \
+            .irqn = LPTMR0_IRQn, \
+        }, \
+    }
 #define TIMER_NUMOF             ((PIT_NUMOF) + (LPTMR_NUMOF))
 
 #define PIT_BASECLOCK           (CLOCK_BUSCLOCK)
@@ -113,6 +114,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART1_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_PTE1,
     },
 };
 

boards/frdm-k64f/include/periph_conf.h

@@ -70,18 +70,26 @@ static const clock_config_t clock_config = {
  * @{
  */
 #define PIT_NUMOF               (2U)
-#define PIT_CONFIG {                 \
-        {                            \
-            .prescaler_ch = 0,       \
-            .count_ch = 1,           \
-        },                           \
-        {                            \
-            .prescaler_ch = 2,       \
-            .count_ch = 3,           \
-        },                           \
+#define PIT_CONFIG {            \
+        {                       \
+            .prescaler_ch = 0,  \
+            .count_ch = 1,      \
+        },                      \
+        {                       \
+            .prescaler_ch = 2,  \
+            .count_ch = 3,      \
+        },                      \
+    }
+#define LPTMR_NUMOF             (1U)
+#define LPTMR_CONFIG { \
+        { \
+            .dev = LPTMR0, \
+            .base_freq = 32768u, \
+            .llwu = LLWU_WAKEUP_MODULE_LPTMR0, \
+            .src = 2, \
+            .irqn = LPTMR0_IRQn, \
+        }, \
     }
-#define LPTMR_NUMOF             (0U)
-#define LPTMR_CONFIG {}
 #define TIMER_NUMOF             ((PIT_NUMOF) + (LPTMR_NUMOF))
 
 #define PIT_BASECLOCK           (CLOCK_BUSCLOCK)
@@ -107,6 +115,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
 };
 

boards/frdm-kw41z/board.c

@@ -23,6 +23,42 @@
 
 void board_init(void)
 {
+    bit_set32(&SIM->SCGC5, SIM_SCGC5_DCDC_SHIFT);
+
+    /* We don't have a status bit for checking if the DCDC is in bypass mode
+     * so we check if the PSWITCH bit is set, assuming that the power switch
+     * has not been released since the DCDC was started. This is run early in
+     * the boot process so it should be fine. */
+    if (DCDC->REG0 & DCDC_REG0_PSWITCH_STATUS_MASK) {
+        /* DCDC is on */
+        /* Spin until DCDC output is stable */
+        while (!(DCDC->REG0 & DCDC_REG0_DCDC_STS_DC_OK_MASK)) {}
+        /* Set up DCDC for pulsed mode in VLPS, LLS */
+        DCDC->REG0 = (DCDC->REG0 & ~(DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK | DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK)) |
+            DCDC_REG0_DCDC_VBAT_DIV_CTRL(0b10) | /* provide VBAT/2 to ADC input to measure battery level */
+            DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK;
+        DCDC->REG1 = DCDC->REG1 |
+            DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK |
+            DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK;
+        DCDC->REG2 = DCDC->REG2 |
+            DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK;
+        DCDC->REG3 = (DCDC->REG3 &
+            ~(DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK |
+              DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK |
+              DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK)) |
+            DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK;
+
+        /* Spin until DCDC is stable */
+        while (!(DCDC->REG0 & DCDC_REG0_DCDC_STS_DC_OK_MASK)) {}
+
+        /* DCDC has stabilized, halt stepping
+         * This must be set before entering low power modes */
+        DCDC->REG3 |= DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK |
+            DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK;
+
+        /* Spin until DCDC is stable */
+        while (!(DCDC->REG0 & DCDC_REG0_DCDC_STS_DC_OK_MASK)) {}
+    }
     /* initialize the CPU core */
     cpu_init();
 

boards/frdm-kw41z/include/periph_conf.h

@@ -87,10 +87,11 @@ static const clock_config_t clock_config = {
 #define LPTMR_CONFIG { \
         { \
             .dev = LPTMR0, \
-            .irqn = LPTMR0_IRQn, \
-            .src = 2, \
             .base_freq = 32768u, \
-        } \
+            .llwu = LLWU_WAKEUP_MODULE_LPTMR0, \
+            .src = 2, \
+            .irqn = LPTMR0_IRQn, \
+        }, \
     }
 #define TIMER_NUMOF             ((PIT_NUMOF) + (LPTMR_NUMOF))
 #define PIT_BASECLOCK           (CLOCK_BUSCLOCK)
@@ -114,6 +115,13 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_LPUART,
+        /* Undocumented behavior: LPUART fails to detect the START bit at wake up
+         * with LLWU sometimes. This seem to be related to using the builtin
+         * DCDC for powering the MCU. */
+        /* LLWU_WAKEUP_PIN_PTC6 is the correct setting on this dev board if you
+         * want to try using LLS mode, or if it does not matter that the UART RX
+         * byte is sometimes is corrupt */
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
 };
 #define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))

boards/mulle/include/periph_conf.h

@@ -106,10 +106,11 @@ static const clock_config_t clock_config = {
 #define LPTMR_CONFIG { \
         { \
             .dev = LPTMR0, \
-            .irqn = LPTMR0_IRQn, \
-            .src = 2, \
             .base_freq = 32768u, \
-        } \
+            .llwu = LLWU_WAKEUP_MODULE_LPTMR0, \
+            .src = 2, \
+            .irqn = LPTMR0_IRQn, \
+        }, \
     }
 #define TIMER_NUMOF             ((PIT_NUMOF) + (LPTMR_NUMOF))
 
@@ -137,6 +138,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
     {
         .dev    = UART1,
@@ -150,6 +152,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART1_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_PTC3,
     },
 };
 

boards/pba-d-01-kw2x/include/periph_conf.h

@@ -108,6 +108,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART2_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
     {
         .dev    = UART0,
@@ -121,6 +122,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     }
 };
 

boards/teensy31/include/periph_conf.h

@@ -113,6 +113,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
     {
         .dev    = UART1,
@@ -126,6 +127,7 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC4_UART1_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_UART,
+        .llwu_rx = LLWU_WAKEUP_PIN_PTC3,
     },
 };
 

boards/usb-kw41z/include/periph_conf.h

@@ -87,10 +87,11 @@ static const clock_config_t clock_config = {
 #define LPTMR_CONFIG { \
         { \
             .dev = LPTMR0, \
-            .irqn = LPTMR0_IRQn, \
-            .src = 2, \
             .base_freq = 32768u, \
-        } \
+            .llwu = LLWU_WAKEUP_MODULE_LPTMR0, \
+            .src = 2, \
+            .irqn = LPTMR0_IRQn, \
+        }, \
     }
 #define TIMER_NUMOF             ((PIT_NUMOF) + (LPTMR_NUMOF))
 #define PIT_BASECLOCK           (CLOCK_BUSCLOCK)
@@ -114,6 +115,10 @@ static const uart_conf_t uart_config[] = {
         .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
         .mode   = UART_MODE_8N1,
         .type   = KINETIS_LPUART,
+        /* LLWU_WAKEUP_PIN_PTC6 is the correct setting on this dev board if you
+         * want to try using LLS mode. The current setting will block LLS mode
+         * if UART RX is used, which is true in most applications */
+        .llwu_rx = LLWU_WAKEUP_PIN_UNDEF,
     },
 };
 #define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))

cpu/kinetis/Makefile.features

@@ -2,6 +2,7 @@ FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_hwrng
 FEATURES_PROVIDED += periph_gpio
 FEATURES_PROVIDED += periph_gpio_irq
+FEATURES_PROVIDED += periph_llwu
 FEATURES_PROVIDED += periph_mcg
 
 include $(RIOTCPU)/cortexm_common/Makefile.features

cpu/kinetis/Makefile.include

@@ -36,10 +36,14 @@ export UNDEF += $(BINDIR)/cpu/fcfield.o
 # include common periph drivers
 USEMODULE += periph_common
 
-# select kinetis periph drivers
+# select Kinetis periph drivers
+USEMODULE += periph_llwu
 USEMODULE += periph_mcg
 USEMODULE += periph_wdog
 
+# Enable power management by default
+USEMODULE += pm_layered
+
 # Define a recipe to build the watchdog disable binary, used when flashing
 $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin: $(RIOTCPU)/$(CPU)/dist/wdog-disable.s
 	$(Q)$(MAKE) -C $(RIOTCPU)/$(CPU)/dist/ $(notdir $@)

cpu/kinetis/cpu.c

@@ -22,6 +22,11 @@
 #ifdef MODULE_PERIPH_MCG
 #include "mcg.h"
 #endif
+#if defined(MODULE_PERIPH_LLWU)
+#include "llwu.h"
+#elif defined(MODULE_PM_LAYERED)
+#include "pm_layered.h"
+#endif
 
 /**
  * @brief Initialize the CPU, set IRQ priorities
@@ -39,6 +44,16 @@ void cpu_init(void)
     /* initialize the CPU clocking provided by the MCG module */
     kinetis_mcg_init();
 #endif
+
+#if defined(MODULE_PERIPH_LLWU)
+    /* initialize the LLWU module for sleep/wakeup management */
+    llwu_init();
+#elif defined(MODULE_PM_LAYERED)
+    /* Block LLS mode since we are not using the LLWU module, which is required
+     * to be able to wake up from LLS */
+    pm_block(KINETIS_PM_LLS);
+#endif
+
     /* trigger static peripheral initialization */
     periph_init();
 }