Remove base instances from custom cells

RTimothyEdwards · Oct 17, 2023 · 310ef1c · 310ef1c
1 parent 6bf520c
commit 310ef1c
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Showing 4 changed files with 21 additions and 38 deletions.
diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__decap_12.v
@@ -45,12 +45,12 @@ module sky130_ef_sc_hd__decap_12 (
     VNB
 );
 
+    // Module ports
     input VPWR;
     input VGND;
     input VPB ;
     input VNB ;
     // No contents.
-
 endmodule
 `endcelldefine
 
@@ -70,6 +70,7 @@ endmodule
 
 `celldefine
 module sky130_ef_sc_hd__decap_12 ();
+
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v
@@ -27,8 +27,7 @@
  * every pin without making a connection.  If the net needs an antenna
  * tiedown, the fakediode cell can be replaced by the real diode cell.
  *
- * Verilog wrapper for diode with size of 2 units.  Note that the wrapper
- * is around the original SkyWater diode base cell;  because the diode
+ * Verilog wrapper for diode with size of 2 units. Because the diode
  * has no function in verilog, there is no difference between the verilog
  * definitions of the diode and fake diode other than the cell name.
  *
@@ -50,19 +49,13 @@ module sky130_ef_sc_hd__fakediode_2 (
     VNB
 );
 
+    // Module ports
     input DIODE;
     input VPWR ;
     input VGND ;
     input VPB  ;
     input VNB  ;
-    sky130_fd_sc_hd__diode base (
-        .DIODE(DIODE),
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPB),
-        .VNB(VNB)
-    );
-
+     // No contents.
 endmodule
 `endcelldefine
 
@@ -75,18 +68,15 @@ module sky130_ef_sc_hd__fakediode_2 (
     DIODE
 );
 
+    // Module ports
     input DIODE;
 
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;
     supply1 VPB ;
     supply0 VNB ;
-
-    sky130_fd_sc_hd__diode base (
-        .DIODE(DIODE)
-    );
-
+     // No contents.
 endmodule
 `endcelldefine
 

diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_12.v
@@ -35,23 +35,17 @@
 
 `celldefine
 module sky130_ef_sc_hd__fill_12 (
-    VPWR ,
-    VGND ,
-    VPB  ,
+    VPWR,
+    VGND,
+    VPB ,
     VNB
 );
 
-    input VPWR ;
-    input VGND ;
-    input VPB  ;
-    input VNB  ;
-    sky130_fd_sc_hd__fill base (
-        .VPWR(VPWR),
-        .VGND(VGND),
-        .VPB(VPB),
-        .VNB(VNB)
-    );
-
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    // No contents.
 endmodule
 `endcelldefine
 
@@ -60,18 +54,14 @@ endmodule
 /*********************************************************/
 
 `celldefine
-module sky130_ef_sc_hd__fill_12 (
-);
+module sky130_ef_sc_hd__fill_12 ();
 
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;
     supply1 VPB ;
     supply0 VNB ;
-
-    sky130_fd_sc_hd__fill base (
-    );
-
+    // No contents.
 endmodule
 `endcelldefine
 

diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_8.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_8.v
@@ -41,11 +41,12 @@ module sky130_ef_sc_hd__fill_8 (
     VNB
 );
 
+    // Module ports
     input VPWR;
     input VGND;
     input VPB ;
     input VNB ;
-
+    // No contents.
 endmodule
 `endcelldefine
 
@@ -55,12 +56,13 @@ endmodule
 
 `celldefine
 module sky130_ef_sc_hd__fill_8 ();
+
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;
     supply1 VPB ;
     supply0 VNB ;
-
+    // No contents.
 endmodule
 `endcelldefine