Welcome to the Rydev Blog code repository. Here you will find all the resources and documentation needed to understand and navigate the project.
- Project Description
- Getting Started
- Tests
- Deployment
- Contributing
- License
Rydev Blog is designed to showcase our progress in ASIC and FPGA Design and Verification to the community. So that anyone interested can delve into this world with the latest tools.
These are the steps to set up the project locally...
- You can run this repo on both Windows and Linux. This project will use open software to simulate and test the designs.
- Clone the repository
git clone https://github.com/username/rydev-blog.git
For more information please go to the wiki, currently in development Simulate RTL Designs with Ease
Open source.