Rebasing lost commits in chisel3_port (chipsalliance#3197)

* refactor ROMGenerator to chisel3. (chipsalliance#3091)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Arbiters to chisel3 (chipsalliance#3092)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ResetCatchAndSync to chisel3. (chipsalliance#3093)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor ReorderQueue to chisel3. (chipsalliance#3094)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* refactor MuxLiteral to chisel3. (chipsalliance#3098)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Counters to chisel3 (chipsalliance#3101)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port CLINT.scala to Chisel 3 (chipsalliance#3107)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/HellaQueue.scala to Chisel3 (chipsalliance#3108)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/IDecode to chisel3 (chipsalliance#3119)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/Frontend to chisel3 (chipsalliance#3118)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port util/ECC.scala to Chisel 3 (chipsalliance#3132)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/CRC to chisel3 (chipsalliance#3129)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port tile/fpu to chisel3 (chipsalliance#3127)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Refactor util/Broadcaster to chisel3 (chipsalliance#3102)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Fix HellaQueue IO type and imcomplete connections (chipsalliance#3157)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/RocketCore to chisel3 (chipsalliance#3121)

* Port rocket/RocketCore to chisel3

* WireInit -> WireDefault

* Try to fix unconnected id_scie_decoder

* Drop all implicit conversions in RocketCore

* Update src/main/scala/rocket/RocketCore.scala

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/NBDCache to chisel3 (chipsalliance#3117)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/ScratchpadSlavePort to chisel3 (chipsalliance#3115)

* Port rocket/ScratchpadSlavePort to chisel3

* Fix missing cloneType in ScratchpadSlavePort

* Fix MuxLookup hardware types in ScratchpadSlavePort

* Fix partial connection in ScratchpadSlavePort
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Port rocket/TLB to Chisel3 (chipsalliance#3114)

* Port rocket/TLB to chisel3

* Remove implicit conversions in TLB
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: SingularityKChen <chency_singularity@163.com>
Co-authored-by: rvsv39 <90169450+rvsv39@users.noreply.github.com>
Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
Co-authored-by: Sharzy <me@sharzy.in>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

src/main/scala/devices/tilelink/CLINT.scala

@@ -2,7 +2,8 @@
 
 package freechips.rocketchip.devices.tilelink
 
-import Chisel._
+import chisel3._
+import chisel3.util.ShiftRegister
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -62,15 +63,15 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
     require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
 
     val io = IO(new Bundle {
-      val rtcTick = Bool(INPUT)
+      val rtcTick = Input(Bool())
     })
 
-    val time = RegInit(UInt(0, width = timeWidth))
-    when (io.rtcTick) { time := time + UInt(1) }
+    val time = RegInit(0.U(timeWidth.W))
+    when (io.rtcTick) { time := time + 1.U }
 
     val nTiles = intnode.out.size
-    val timecmp = Seq.fill(nTiles) { Reg(UInt(width = timeWidth)) }
-    val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
+    val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) }
+    val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
 
     val (intnode_out, _) = intnode.out.unzip
     intnode_out.zipWithIndex.foreach { case (int, i) =>

src/main/scala/rocket/IDecode.scala

@@ -3,7 +3,8 @@
 
 package freechips.rocketchip.rocket
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.tile.HasCoreParameters
 import freechips.rocketchip.util._
@@ -27,21 +28,21 @@ class IntCtrlSigs extends Bundle {
   val rxs2 = Bool()
   val rxs1 = Bool()
   val scie = Bool()
-  val sel_alu2 = Bits(width = A2_X.getWidth)
-  val sel_alu1 = Bits(width = A1_X.getWidth)
-  val sel_imm = Bits(width = IMM_X.getWidth)
+  val sel_alu2 = Bits(A2_X.getWidth.W)
+  val sel_alu1 = Bits(A1_X.getWidth.W)
+  val sel_imm = Bits(IMM_X.getWidth.W)
   val alu_dw = Bool()
-  val alu_fn = Bits(width = FN_X.getWidth)
+  val alu_fn = Bits(FN_X.getWidth.W)
   val mem = Bool()
-  val mem_cmd = Bits(width = M_SZ)
+  val mem_cmd = Bits(M_SZ.W)
   val rfs1 = Bool()
   val rfs2 = Bool()
   val rfs3 = Bool()
   val wfd = Bool()
   val mul = Bool()
   val div = Bool()
   val wxd = Bool()
-  val csr = Bits(width = CSR.SZ)
+  val csr = Bits(CSR.SZ.W)
   val fence_i = Bool()
   val fence = Bool()
   val amo = Bool()