implement #176 DebugPlugin.allowEBreak is now disabled until the debu…

…g bus is used.
SpinalHDL · Apr 20, 2021 · bfe65da · bfe65da
1 parent 4e41654
commit bfe65da
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Showing 2 changed files with 7 additions and 3 deletions.
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -226,6 +226,9 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
       val isPipBusy = RegNext(stages.map(_.arbitration.isValid).orR || iBusFetcher.incoming())
       val godmode = RegInit(False) setWhen(haltIt && !isPipBusy)
       val haltedByBreak = RegInit(False)
+      val allowEBreak = RegInit(False) setWhen(io.bus.cmd.valid)
+//      val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine()
+
 
       val hardwareBreakpoints = Vec(Reg(new Bundle{
         val valid = Bool()
@@ -277,8 +280,6 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
         }
       }
 
-      val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine()
-
       decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) && allowEBreak
       when(execute.arbitration.isValid && execute.input(DO_EBREAK)){
         execute.arbitration.haltByOther := True

diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
@@ -2824,13 +2824,16 @@ class DebugPlugin : public SimElement{
 	socklen_t addr_size;
 	char buffer[1024];
 	uint32_t timeSpacer = 0;
-	bool taskValid = false;
+	bool taskValid;
 	DebugPluginTask task;
 
 
 	DebugPlugin(Workspace* ws){
 		this->ws = ws;
 		this->top = ws->top;
+		taskValid = true; //true as a Workaround to enable the ebreak
+		task.wr = false;
+		task.address = 0;
 
 		#ifdef DEBUG_PLUGIN_EXTERNAL
 			ws->mTimeCmp = ~0;