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Merge branch 'develop'
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deathaxe committed Oct 9, 2024
2 parents 8410a14 + d58fc82 commit 18b405f
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Showing 26 changed files with 64 additions and 27 deletions.
4 changes: 2 additions & 2 deletions .github/workflows/ci.yaml
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Expand Up @@ -14,8 +14,8 @@ jobs:
with:
python-version-file: '.python-version'

- name: Install dependencies
run: python -m pip install -U -r requirements-dev.txt
- name: Install Black
run: python -m pip install -U black

- name: Check formatting
run: python -m black --check .
51 changes: 30 additions & 21 deletions icons/icons.json
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Expand Up @@ -3198,6 +3198,20 @@
}
]
},
"file_type_systemverilog": {
"color": "blue",
"syntaxes": [
{
"extensions": [
"sv",
"svh",
"vh"
],
"name": "Plain Text (SystemVerilog)",
"scope": "source.systemverilog"
}
]
},
"file_type_taskfile": {
"aliases": [
{
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"syntaxes": [
{
"extensions": [
"tailwind.css"
"tailwind.css",
"tailwind.pcss",
"tailwind.postcss"
],
"name": "Plain Text (Tailwind CSS)",
"scope": "source.css.tailwind"
"scope": "source.css.tailwind, source.postcss.tailwind"
}
]
},
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"syntaxes": [
{
"extensions": [
"v",
"vlang"
],
"name": "Plain Text (V)",
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],
"color": "sky"
},
"file_type_verilog": {
"color": "blue",
"syntaxes": [
{
"extensions": [
"v"
],
"name": "Plain Text (Verilog)",
"scope": "source.verilog"
}
]
},
"file_type_vhdl": {
"color": "blue",
"syntaxes": [
Expand All @@ -3632,24 +3659,6 @@
],
"name": "Plain Text (VHDL)",
"scope": "source.vhdl"
},
{
"extensions": [
"sv",
"v",
"svh",
"vh"
],
"name": "Plain Text (SystemVerilog)",
"scope": "source.systemverilog"
},
{
"extensions": [
"v",
"V"
],
"name": "Plain Text (Verilog)",
"scope": "source.verilog"
}
]
},
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3 changes: 3 additions & 0 deletions icons/svg/file_type_systemverilog.svg
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3 changes: 3 additions & 0 deletions icons/svg/file_type_verilog.svg
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12 changes: 12 additions & 0 deletions preferences/file_type_systemverilog.tmPreferences
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@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
<dict>
<key>scope</key>
<string>source.systemverilog</string>
<key>settings</key>
<dict>
<key>icon</key>
<string>file_type_systemverilog</string>
</dict>
</dict>
</plist>
2 changes: 1 addition & 1 deletion preferences/file_type_tailwind.tmPreferences
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Expand Up @@ -2,7 +2,7 @@
<plist version="1.0">
<dict>
<key>scope</key>
<string>source.css.tailwind, source.js.tailwind, source.ts.tailwind</string>
<string>source.css.tailwind, source.js.tailwind, source.postcss.tailwind, source.ts.tailwind</string>
<key>settings</key>
<dict>
<key>icon</key>
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12 changes: 12 additions & 0 deletions preferences/file_type_verilog.tmPreferences
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@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
<dict>
<key>scope</key>
<string>source.verilog</string>
<key>settings</key>
<dict>
<key>icon</key>
<string>file_type_verilog</string>
</dict>
</dict>
</plist>
2 changes: 1 addition & 1 deletion preferences/file_type_vhdl.tmPreferences
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Expand Up @@ -2,7 +2,7 @@
<plist version="1.0">
<dict>
<key>scope</key>
<string>source.systemverilog, source.verilog, source.vhdl</string>
<string>source.vhdl</string>
<key>settings</key>
<dict>
<key>icon</key>
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2 changes: 0 additions & 2 deletions requirements-dev.txt
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@@ -1,5 +1,3 @@
pip

# Build
cairosvg >= 2.7.0
pypng >= 0.20220715.0
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