fixes #349 add support for STM8L101 Low Density device family

Makefile

@@ -32,6 +32,7 @@ build: words
 	make BOARD=XY-LPWM
 	make BOARD=MINDEV
 	make BOARD=SWIMCOM
+	make BOARD=STM8L101F3
 	make BOARD=STM8L051F3
 	make BOARD=STM8L-DISCOVERY
 	make BOARD=STM8S105K4

README.md

@@ -35,9 +35,10 @@ Generic target binaries are provided as for use or for evaluation:
 * [STM8S105K4](https://github.com/TG9541/stm8ef/tree/master/STM8S105K4) for STM8S Medium Density devices (Value or Access Line) with 2K RAM and up to 32K Flash
 * [STM8S207RB](https://github.com/TG9541/stm8ef/tree/master/STM8S207RB) for STM8S High Density devices (Value or Performance Line) with 6K RAM and up to 32K + 96K Flash
 * [STM8L051F3](https://github.com/TG9541/stm8ef/tree/master/STM8L051F3) for STM8L Low Density devices (see [issue](https://github.com/TG9541/stm8ef/issues/137#issuecomment-354542670))
+* [STM8L101F3](https://github.com/TG9541/stm8ef/tree/master/STM8L101F3) for STM8L101 Low Density devices (experimental, see [issue](https://github.com/TG9541/stm8ef/issues/349))
 * [STM8L-DISCOVERY](https://github.com/TG9541/stm8ef/tree/master/STM8L-DISCOVERY) for STM8L Medium Density devices like STM8L152C6
 
-Various STM8 Discovery boards and [breakout boards](https://github.com/TG9541/stm8ef/wiki/Breakout-Boards) for Low-, Medium-, and High-Density devices can be used. STM8L devices are supported but there is currently no support for STM8L101F3 or STM8L001J3.
+Various STM8 Discovery boards and [breakout boards](https://github.com/TG9541/stm8ef/wiki/Breakout-Boards) for Low-, Medium-, and High-Density devices can be used. Support for STM8L devices is work-in-progress (especially the latest additions STM8L101F3 and STM8L001J3 are  experimental).
 
 ## Board support:
 

STM8L051F3/boardcore.inc

@@ -52,7 +52,7 @@ BKEYCHAR:
 ;===============================================================
 
 ;       BOARDINIT  ( -- )
-;       Init board GPIO (except COM ports)
+;       Init board GPIO
 
 BOARDINIT:
         ; Board I/O initialization: enable USART TX->PA2, RX->PA3

STM8L101F3/README.md

@@ -0,0 +1,9 @@
+#STM8L101F3P6 Base Image
+
+Expertimental image for STM8L101F3P6. Most things, including NVM and the BG task should work.
+
+![stm8l101f3p6_](https://user-images.githubusercontent.com/5466977/93720666-d7a20680-fb8a-11ea-88c0-6cb7e09e1f20.png)
+
+The STM8L001J3M3 is even more experimental - it may brick your chip!.
+
+In order to make the binary compatible with the STM8L001J3M3 the TX pin uses low-side GPIO settings (i.e. it requires a pull-up).

STM8L101F3/boardcore.inc

@@ -0,0 +1,63 @@
+; STM8L101F3P6 "Core" STM8L device dependent routine default code
+
+; Note: for supporting a new board create a new board configuration
+;       folder with a "globconfig.inc" and a copy of this file.
+
+; ==============================================
+
+        .ifne   HAS_LED7SEG
+;       LED_MPX driver ( -- )
+;       Code called from ISR for LED MPX
+
+LED_MPX:
+        RET
+        .endif
+
+; ==============================================
+
+        .ifne   HAS_OUTPUTS
+;       OUT!  ( c -- )
+;       Put c to board outputs, storing a copy in OUTPUTS
+        .dw     LINK
+
+        LINK =  .
+        .db     (4)
+        .ascii  "OUT!"
+OUTSTOR:
+        RET
+        .endif
+
+;===============================================================
+
+        .ifne   HAS_KEYS
+;       BKEY  ( -- f )     ( TOS STM8: -- A,Z,N )
+;       Read board key state as a bitfield
+        .dw     LINK
+
+        LINK =  .
+        .db     (4)
+        .ascii  "BKEY"
+BKEY:
+        CLR     A
+        JP      ASTOR
+
+
+;       BKEYC  (  -- c )   ( TOS STM8: -- A,Z,N )
+;       Read and translate board dependent key bitmap into char
+
+BKEYCHAR:
+        JRA     BKEY            ; Dummy: get "no key" and leave it as it is
+       .endif
+
+;===============================================================
+
+;       BOARDINIT  ( -- )
+;       Init board GPIO
+
+BOARDINIT:
+        ; Clock init: enable TIM2 and USART clock
+        MOV     CLK_PCKENR1,#0x21
+        ; Board I/O for UART: enable USART push/pull (careful with STM8L001J3!)
+;        BSET    PC_DDR,#3        ; TX->PC3, RX->PC2
+;        BSET    PC_CR1,#3
+        RET

STM8L101F3/globconf.inc

@@ -0,0 +1,41 @@
+; STM8EF Global Configuration File
+; Config for STM8L101F3
+; Clock: HSI (no crystal)
+
+        HALF_DUPLEX      = 0    ; Use UART in half duplex mode
+        HAS_TXUART       = 1    ; UART TXD, word TX!
+        HAS_RXUART       = 1    ; UART RXD, word ?RX
+        HAS_TXSIM        = 0    ; Enable TxD via GPIO/TIM4, word TXGP!
+        HAS_RXSIM        = 0    ; Enable RxD via GPIO/TIM4, word ?RXGP
+        PNRX             = 0    ; Port GPIO# for HAS_RXDSIM
+        PNTX             = 0    ; Port GPIO# for HAS_TXDSIM
+
+        EMIT_BG  = DROP         ; 7S-LED background EMIT vector
+        QKEY_BG  = ZERO         ; Board keys background QKEY vector
+
+        HAS_LED7SEG      = 0    ; no 7S-Display
+        HAS_KEYS         = 0    ; no keys on module
+        HAS_OUTPUTS      = 0    ; yes, one LED
+        HAS_ADC          = 0    ; Analog input words
+
+        HAS_BACKGROUND   = 1    ; Background Forth task (TIM2 ticker)
+        HAS_CPNVM        = 1    ; Can compile to Flash, always interpret to RAM
+        HAS_DOES         = 1    ; CREATE-DOES> extension
+        HAS_DOLOOP       = 1    ; DO .. LOOP extension: DO LEAVE LOOP +LOOP
+
+
+        CASEINSENSITIVE  = 1    ; Case insensitive dictionary search
+        SPEEDOVERSIZE    = 0    ; Speed-over-size in core words: ROT - = <
+        BAREBONES        = 0    ; Remove or unlink some more: hi HERE .R U.R SPACES @EXECUTE AHEAD CALL, EXIT COMPILE [COMPILE]
+
+        WORDS_LINKINTER  = 0    ; Link interpreter words: ACCEPT QUERY TAP kTAP hi 'BOOT tmp >IN 'TIB #TIB eval CONTEXT pars PARSE NUMBER? DIGIT? WORD TOKEN NAME> SAME? find ABORT aborq $INTERPRET INTER? .OK ?STACK EVAL PRESET QUIT $COMPILE
+        WORDS_LINKCOMP   = 0    ; Link compiler words: cp last OVERT $"| ."| $,n
+        WORDS_LINKRUNTI  = 0    ; Link runtime words: doLit do$ doVAR donxt dodoes ?branch branch
+        WORDS_LINKCHAR   = 1    ; Link char out words: DIGIT <# # #S SIGN #> str hld HOLD
+        WORDS_LINKMISC   = 0    ; Link composing words of SEE DUMP WORDS: >CHAR _TYPE dm+ .ID >NAME
+
+        WORDS_EXTRASTACK = 0    ; Link/include stack core words: rp@ rp! sp! sp@ DEPTH
+        WORDS_EXTRADEBUG = 0    ; Extra debug words: SEE
+        WORDS_EXTRACORE  = 1    ; Extra core words: =0 I
+        WORDS_EXTRAMEM   = 1    ; Extra memory words: B! 2C@ 2C!
+        WORDS_EXTRAEEPR  = 0    ; Extra EEPROM lock/unlock words: LOCK ULOCK ULOCKF LOCKF

STM8L101F3/stm8device.h

@@ -0,0 +1,33 @@
+#define STM8L
+
+// #define INTVEC_TLI            0
+#define INTVEC_FLASH          1
+// #define INTVEC_DMA1_01        2
+// #define INTVEC_DMA1_23        3
+#define INTVEC_AWU            4
+// #define INTVEC_PVD            5
+#define INTVEC_EXTIB          6
+#define INTVEC_EXTID          7
+#define INTVEC_EXTI0          8
+#define INTVEC_EXTI1          9
+#define INTVEC_EXTI2         10
+#define INTVEC_EXTI3         11
+#define INTVEC_EXTI4         12
+#define INTVEC_EXTI5         13
+#define INTVEC_EXTI6         14
+#define INTVEC_EXTI7         15
+// #define INTVEC_CLK           17
+// #define INTVEC_LCD           16  // STM8L152
+#define INTVEC_COMP          18
+#define INTVEC_TIM2_UPDATE   19
+#define INTVEC_TIM2_CAPCOM   20
+#define INTVEC_TIM3_UPDATE   21
+#define INTVEC_TIM3_CAPCOM   22
+// #define INTVEC_RI            23  // STM8L051F3
+// #define INTVEC_TIM1_UPDATE   23  // STM8L151, STM8L152
+// #define INTVEC_TIM1_CAPCOM   24
+#define INTVEC_TIM4          25
+#define INTVEC_SPI1          26
+#define INTVEC_USART1_TXD    27
+#define INTVEC_USART1_RXD    28
+#define INTVEC_I2C1          29

STM8L101F3/target.inc

@@ -0,0 +1,14 @@
+;       STM8L101F3 device and memory layout configuration
+
+        TARGET = STM8L101F3     ; Not quite the same as STM8L051F3
+
+        RAMEND =        0x05FF  ; "RAMEND" system (return) stack, growing down
+        EEPROMBASE =    0x1000  ; "EESTART" EEPROM start address (not really)
+        EEPROMEND =     0x10FF  ; "EEEND" 256 bytes EEPROM (see datasheet...)
+        FLASHEND =      0x9FFF  ; "FLASHEND" 8K devices
+
+        FORTHRAM =      0x0030  ; Start of RAM controlled by Forth
+        UPPLOC  =       0x0060  ; UPP (user/system area) location for 1K RAM
+        CTOPLOC =       0x0080  ; CTOP (user dictionary) location for 1K RAM
+        SPPLOC  =       0x0550  ; SPP (data stack top), TIB start (rather 0x0550)
+        RPPLOC  =       RAMEND  ; RPP (return stack top)

forth.asm

@@ -107,14 +107,16 @@
         STM8S_LOD        = 103  ; STM8S Low Density
         STM8S_MED        = 105  ; STM8S Medium Density
         STM8S_HID        = 207  ; STM8S High Density
-        STM8L_LOD        = 051  ; STM8L Low Density
+        STM8L_LOD        = 051  ; STM8L Low Density, RM0031 family
+        STM8L_101        = 101  ; STM8L Low Density, RM0013 family
         STM8L_MHD        = 152  ; STM8L Medium and High Density
 
         ; STM8 family flags
         STM8S            = 0    ; FAMILY: STM8S device
         STM8L            = 1    ; FAMILY: STM8L device
 
         ; legacy chip type (deprecated - preferably use the chip type constants)
+        STM8L101F3 = STM8L_101  ; L core, 8K flash incl EEPROM, 1.5K RAM, UART1
         STM8L051F3 = STM8L_LOD  ; L core, 8K flash, 1K RAM, 256 EEPROM, UART1
         STM8L152C6 = STM8L_MHD  ; L core, 32K flash, 2K RAM, 1K EEPROM, UART1
         STM8S003F3 = STM8S_LOD  ; 8K flash, 1K RAM, 128 EEPROM, UART1
@@ -140,7 +142,7 @@
           FAMILY = STM8S
           .include  "stm8device.inc"
         .endif
-        .ifeq   (TARGET - STM8L_LOD) * (TARGET - STM8L_MHD)
+        .ifeq   (TARGET - STM8L_101) * (TARGET - STM8L_LOD) * (TARGET - STM8L_MHD)
           FAMILY = STM8L
           .include  "stm8ldevice.inc"
         .endif

inc/stm8ldevice.inc

@@ -284,6 +284,27 @@
  TIM2_CR2 = 0x5251 ; TIM2 control register 2 0x00
  TIM2_SMCR = 0x5252 ; TIM2 Slave mode control register  0x00
  TIM2_ETR = 0x5253 ; TIM2 external trigger register 0x00
+        .ifeq   (TARGET - STM8L_101)
+        ; STM8L101 family devices have an offset shift here
+ TIM2_IER = 0x5254 ; TIM2 interrupt enable register  0x00
+ TIM2_SR1 = 0x5255 ; TIM2 status register 1 0x00
+ TIM2_SR2 = 0x5256 ; TIM2 status register 2 0x00
+ TIM2_EGR = 0x5257 ; TIM2 event generation register  0x00
+ TIM2_CCMR1 = 0x5258 ; TIM2 capture/compare mode register 1 0x00
+ TIM2_CCMR2 = 0x5259 ; TIM2 capture/compare mode register 2 0x00
+ TIM2_CCER1 = 0x525A ; TIM2 capture/compare enable register 1 0x00
+ TIM2_CNTRH = 0x525B ; TIM2 counter high 0x00
+ TIM2_CNTRL = 0x525C ; TIM2 counter low 0x00
+ TIM2_PSCR = 0x525D ; TIM2 prescaler register 0x00
+ TIM2_ARRH = 0x525E ; TIM2 auto-reload register high 0xFF
+ TIM2_ARRL = 0x525F ; TIM2 auto-reload register low 0xFF
+ TIM2_CCR1H = 0x5260 ; TIM2 capture/compare register 1 high 0x00
+ TIM2_CCR1L = 0x5261 ; TIM2 capture/compare register 1 low 0x00
+ TIM2_CCR2H = 0x5262 ; TIM2 capture/compare register 2 high 0x00
+ TIM2_CCR2L = 0x5263 ; TIM2 capture/compare register 2 low 0x00
+ TIM2_BKR = 0x5264 ; TIM2 break register 0x00
+ TIM2_OISR = 0x5265 ; TIM2 output idle state register 0x00
+        .else
  TIM2_DER = 0x5254 ; TIM2 DMA1 request enable register 0x00
  TIM2_IER = 0x5255 ; TIM2 interrupt enable register  0x00
  TIM2_SR1 = 0x5256 ; TIM2 status register 1 0x00
@@ -296,14 +317,14 @@
  TIM2_CNTRL = 0x525D ; TIM2 counter low 0x00
  TIM2_PSCR = 0x525E ; TIM2 prescaler register 0x00
  TIM2_ARRH = 0x525F ; TIM2 auto-reload register high 0xFF
-; TIM2
  TIM2_ARRL = 0x5260 ; TIM2 auto-reload register low 0xFF
  TIM2_CCR1H = 0x5261 ; TIM2 capture/compare register 1 high 0x00
  TIM2_CCR1L = 0x5262 ; TIM2 capture/compare register 1 low 0x00
  TIM2_CCR2H = 0x5263 ; TIM2 capture/compare register 2 high 0x00
  TIM2_CCR2L = 0x5264 ; TIM2 capture/compare register 2 low 0x00
  TIM2_BKR = 0x5265 ; TIM2 break register 0x00
  TIM2_OISR = 0x5266 ; TIM2 output idle state register 0x00
+        .endif
 
 ; 0x00 5267 to 0x00 527F Reserved area (25 bytes)
 
@@ -312,6 +333,27 @@
  TIM3_CR2 = 0x5281 ; TIM3 control register 2 0x00
  TIM3_SMCR = 0x5282 ; TIM3 Slave mode control register  0x00
  TIM3_ETR = 0x5283 ; TIM3 external trigger register 0x00
+        .ifeq   (TARGET - STM8L_101)
+        ; STM8L101 family devices have an offset shift here
+ TIM3_IER = 0x5284 ; TIM3 interrupt enable register  0x00
+ TIM3_SR1 = 0x5285 ; TIM3 status register 1 0x00
+ TIM3_SR2 = 0x5286 ; TIM3 status register 2 0x00
+ TIM3_EGR = 0x5287 ; TIM3 event generation register  0x00
+ TIM3_CCMR1 = 0x5288 ; TIM3 Capture/Compare mode register 1 0x00
+ TIM3_CCMR2 = 0x5289 ; TIM3 Capture/Compare mode register 2 0x00
+ TIM3_CCER1 = 0x528A ; TIM3 Capture/Compare enable register 1 0x00
+ TIM3_CNTRH = 0x528B ; TIM3 counter high 0x00
+ TIM3_CNTRL = 0x528C ; TIM3 counter low 0x00
+ TIM3_PSCR = 0x528D ; TIM3 prescaler register 0x00
+ TIM3_ARRH = 0x528E ; TIM3 Auto-reload register high 0xFF
+ TIM3_ARRL = 0x528F ; TIM3 Auto-reload register low 0xFF
+ TIM3_CCR1H = 0x5290 ; TIM3 Capture/Compare register 1 high 0x00
+ TIM3_CCR1L = 0x5291 ; TIM3 Capture/Compare register 1 low 0x00
+ TIM3_CCR2H = 0x5292 ; TIM3 Capture/Compare register 2 high 0x00
+ TIM3_CCR2L = 0x5293 ; TIM3 Capture/Compare register 2 low 0x00
+ TIM3_BKR = 0x5294 ; TIM3 break register 0x00
+ TIM3_OISR = 0x5295 ; TIM3 output idle state register 0x00
+        .else
  TIM3_DER = 0x5284 ; TIM3 DMA1 request enable register 0x00
  TIM3_IER = 0x5285 ; TIM3 interrupt enable register  0x00
  TIM3_SR1 = 0x5286 ; TIM3 status register 1 0x00
@@ -331,19 +373,7 @@
  TIM3_CCR2L = 0x5294 ; TIM3 Capture/Compare register 2 low 0x00
  TIM3_BKR = 0x5295 ; TIM3 break register 0x00
  TIM3_OISR = 0x5296 ; TIM3 output idle state register 0x00
-; 0x00 5297 to 0x00 52DF Reserved area (72 bytes)
-; TIM4
- TIM4_CR1 = 0x52E0 ; TIM4 control register 1 0x00
- TIM4_CR2 = 0x52E1 ; TIM4 control register 2 0x00
- TIM4_SMCR = 0x52E2 ; TIM4 Slave mode control register  0x00
- TIM4_DER = 0x52E3 ; TIM4 DMA1 request enable register 0x00
- TIM4_IER = 0x52E4 ; TIM4 Interrupt enable register  0x00
- TIM4_SR  = 0x52E5 ; TIM4 status register 1 0x00
- TIM4_SR1 = TIM4_SR ; STM8L051F3 data sheet error
- TIM4_EGR = 0x52E6 ; TIM4 Event generation register  0x00
- TIM4_CNTR = 0x52E7 ; TIM4 counter 0x00
- TIM4_PSCR = 0x52E8 ; TIM4 prescaler register  0x00
- TIM4_ARR = 0x52E9 ; TIM4 Auto-reload register 0x00
+        .endif
 
         .ifne   BG_USE_TIM1
         error: BG_USE_TIM1 currently unsupported (please check datasheet)
@@ -365,6 +395,33 @@
         .endif
         .endif
 
+; 0x00 5297 to 0x00 52DF Reserved area (72 bytes)
+
+; TIM4
+ TIM4_CR1 = 0x52E0 ; TIM4 control register 1 0x00
+ TIM4_CR2 = 0x52E1 ; TIM4 control register 2 0x00
+ TIM4_SMCR = 0x52E2 ; TIM4 Slave mode control register  0x00
+        .ifeq   (TARGET - STM8L_101)
+        ; STM8L101 family devices have an offset shift here
+ TIM4_IER = 0x52E3 ; TIM4 Interrupt enable register  0x00
+ TIM4_SR  = 0x52E4 ; TIM4 status register 1 0x00
+ TIM4_SR1 = TIM4_SR ; alias
+ TIM4_EGR = 0x52E5 ; TIM4 Event generation register  0x00
+ TIM4_CNTR = 0x52E6 ; TIM4 counter 0x00
+ TIM4_PSCR = 0x52E7 ; TIM4 prescaler register  0x00
+ TIM4_ARR = 0x52E8 ; TIM4 Auto-reload register 0x00
+        .else
+  TIM4_DER = 0x52E3 ; TIM4 DMA1 request enable register 0x00
+ TIM4_IER = 0x52E4 ; TIM4 Interrupt enable register  0x00
+ TIM4_SR  = 0x52E5 ; TIM4 status register 1 0x00
+ TIM4_SR1 = TIM4_SR ; STM8L051F3 data sheet error
+ TIM4_EGR = 0x52E6 ; TIM4 Event generation register  0x00
+ TIM4_CNTR = 0x52E7 ; TIM4 counter 0x00
+ TIM4_PSCR = 0x52E8 ; TIM4 prescaler register  0x00
+ TIM4_ARR = 0x52E9 ; TIM4 Auto-reload register 0x00
+        .endif
+
+
 ; 0x00 52EA to 0x00 52FE Reserved area (21 bytes)
 ; IRTIM
  IR_CR = 0x52FF ; Infrared control register 0x00

lib/]B!

@@ -10,9 +10,7 @@
 \ ------------------------------------------------------------------------------
 \\ Example:
 
-#require CONSTANT
-
-\res MCU: STM8S103
+\res MCU: STM8S
 
 \res export PB_ODR