#Ethernet FCS Ethernet FCS exercise for course 34349: FPGA design for communication technology at the Technical University of Denmark.

The accompanying report goes through the following:

Task 1

Generate the VHDL for an entity, fcs_check_serial code that checks an Ethernet packet for bit errors, assuming a serial stream

Task 2

Synthesize and perform a Place & Route on the fcs_check_serial entity.

Task 3

Generate a testbench for the fcs_check_serial entity.

Task 4

Redesign the fcs_check_serial and make it parallel, calling it fcs_check_parallel. Do task 2 and 3 also for the new entity.