RISC-V-5-stage-pipelined-in-verilog

RISC-V PIPELINED PROCESSOR IN VERILOG. The Project is done in Embedded system design course for design of 5- stage pipelined RISC-V processor in Verilog supporting all formats of 32IM of RISC-V ISA. Project files of Intel Quartus prime are given.

Note:The project is under construction and I am adding new features like Caches design,Floating point etc.Thank you