A Simple 6502 / 65C02 implementation for Digital
This implementation aims simplicity for educational purposes.
It is fully 6502 and 65C02 compatible and passes all functional and extended opcode tests from Klaus Dormann's test suite, but it is NOT cycle accurate with the original cpu versions. (The actual cycles for each opcode can be seen in the microcode ROM files).
The microcode is generated by a C program and can generate the 6502 or 65C02 microcode. (Use any C compiler, but it has been only tested with GCC.)
The interrupts are handled by injecting the BRK opcode just in the original CPU.
To start open the 6502.dig file in Digital.
The test suite will be loaded into the RAM and the simulation can be started.
(The test suite runs quite a long time but when it finishes it loads ASCII 'E'($45), 'N'($4E), 'D'($44) into the registers A X and Y and the PC loops around $34DE.)
There is also a generic version of the CPU with isolated data bus which can be included as a sub-circuit and configured as either 6502 or 65C02. For examples see 6502test.dig and 65c02test.dig.
In this versions the test suit outputs to the memory mapped data terminal at address $0000.
Unfortunately Digital does not allow to "dive" into a sub-circuit during the simulation, but if you right click on the RAM you can view it's contents updating during the simulation.
You will need:
- Helmut Neemann's Digital simulator to run the circuit
- A C compiler if you want to change the microcode easily
- A 6502 assembler if you want to run your own 6502 code
Inspirations and informations are taken from: