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chore: fpga22: add u280 floorplan directive
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@Blaok
Blaok committed Dec 17, 2021
1 parent b05a04d commit af451dc
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3 changes: 1 addition & 2 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,9 @@ find_package(SDx)
if(SDx_FOUND)
add_tapa_target(
sssp-hw-xo
--enable-synth-util
INPUT src/sssp.cpp
TOP SSSP
CONNECTIVITY ${CMAKE_CURRENT_SOURCE_DIR}/link_config.ini
DIRECTIVE ${CMAKE_CURRENT_SOURCE_DIR}/directive.json
CONSTRAINT ${CMAKE_CURRENT_BINARY_DIR}/constraint.tcl
CLOCK_PERIOD 6.250
PLATFORM xilinx_u280_xdma_201920_3)
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383 changes: 383 additions & 0 deletions directive.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,383 @@
{
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"tcl": "\ncreate_pblock pblock_X4Y4_X7Y7\nresize_pblock pblock_X4Y4_X7Y7 -add CLOCKREGION_X4Y4:CLOCKREGION_X7Y7\nresize_pblock pblock_X4Y4_X7Y7 -remove {\n CLOCKREGION_X7Y0:CLOCKREGION_X7Y11\n}"
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"tcl": "\ncreate_pblock pblock_X4Y0_X7Y3\nresize_pblock pblock_X4Y0_X7Y3 -add CLOCKREGION_X4Y0:CLOCKREGION_X7Y3\nresize_pblock pblock_X4Y0_X7Y3 -remove {\n CLOCKREGION_X7Y0:CLOCKREGION_X7Y11\n}"
}
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]
}

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