Support for wait until idle command in Avalon Master

vunit/vhdl/verification_components/src/avalon_master.vhd

@@ -17,6 +17,7 @@ context work.com_context;
 use work.com_types_pkg.all;
 use work.logger_pkg.all;
 use work.check_pkg.all;
+use work.sync_pkg.all;
 
 library osvvm;
 use osvvm.RandomPkg.all;
@@ -49,6 +50,7 @@ architecture a of avalon_master is
   constant acknowledge_queue : queue_t := new_queue;
   constant burst_acknowledge_queue : queue_t := new_queue;
   constant burstlen_queue : queue_t := new_queue;
+  signal burst_read_flag : boolean := false;
 begin
 
   main : process
@@ -125,6 +127,10 @@ begin
             burstcount(burstcount'range) <= (others => 'U');
           end loop;
 
+        elsif msg_type = wait_until_idle_msg then
+          wait until not burst_read_flag and is_empty(burst_acknowledge_queue) and rising_edge(clk);
+          handle_wait_until_idle(net, msg_type, request_msg);
+
         else
           unexpected_msg_type(msg_type);
         end if;
@@ -160,6 +166,7 @@ begin
     variable burst : positive;
   begin
     wait until readdatavalid = '1' and not is_empty(burst_acknowledge_queue) and rising_edge(clk);
+    burst_read_flag <= true;
     request_msg := pop(burst_acknowledge_queue);
     burst := pop(burstlen_queue);
     reply_msg := new_msg(sender => avmm_burst_rd_actor);
@@ -172,6 +179,7 @@ begin
     end loop;
     reply(net, request_msg, reply_msg);
     delete(request_msg);
+    burst_read_flag <= false;
   end process;
 
 end architecture;

vunit/vhdl/verification_components/test/tb_avalon_master.vhd

@@ -103,6 +103,8 @@ begin
     variable tmp : std_logic_vector(writedata'range);
     variable value : std_logic_vector(writedata'range) := (others => '1');
     variable burst_rd_ref : bus_reference_t;
+    variable bus_rd_ref1 : bus_reference_t;
+    variable bus_rd_ref2 : bus_reference_t;
     type bus_reference_arr_t is array (0 to tb_cfg.transfers-1) of bus_reference_t;
     variable rd_ref : bus_reference_arr_t;
     constant data_queue : queue_t := new_queue;
@@ -241,6 +243,41 @@ begin
         end loop;
       end loop;
 
+    elsif run("wait until idle") then
+      wait_until_idle(net, bus_handle);
+      write_bus(net, bus_handle, 0, value);
+      value := std_logic_vector(to_unsigned(456, value'length));
+      write_bus(net, bus_handle, 0, value);
+      read_bus(net, bus_handle, 4, bus_rd_ref1);
+      read_bus(net, bus_handle, 0, bus_rd_ref2);
+      wait_until_idle(net, bus_handle);
+      await_read_bus_reply(net, bus_rd_ref1, tmp);
+      await_read_bus_reply(net, bus_rd_ref2, tmp);
+      check_equal(tmp, value, "invalid data");
+      wait_until_idle(net, bus_handle);
+      write_bus(net, bus_handle, 0, value);
+      wait_until_idle(net, bus_handle);
+
+      -- Wait till idle during bursts
+      for i in 1 to tb_cfg.transfers loop
+        push(data_queue, std_logic_vector(to_unsigned(i, writedata'length)));
+      end loop;
+      write_bus(net, bus_handle, 0, tb_cfg.transfers, data_queue);
+      wait_until_idle(net, bus_handle);
+      wait until rising_edge(clk);
+      check_equal(write, '0', "unexpected write after wail till idle");
+
+      read_bus(net, bus_handle, 0, tb_cfg.transfers, data_queue);
+      wait_until_idle(net, bus_handle);
+      wait until rising_edge(clk);
+      check_equal(readdatavalid, '0', "unexpected readdatavalid after wail till idle");
+
+      read_bus(net, bus_handle, 0, tb_cfg.transfers, burst_rd_ref);
+      wait_until_idle(net, bus_handle);
+      wait until rising_edge(clk);
+      check_equal(readdatavalid, '0', "unexpected readdatavalid after wail till idle");
+      await_read_bus_reply(net, bus_handle, data_queue, burst_rd_ref);
+      wait_until_idle(net, bus_handle);
 
     end if;