Group signal assignments a little more logically

VUnit · Mar 11, 2024 · 2e6846f · 2e6846f
1 parent e44b235
commit 2e6846f
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/vunit/vhdl/verification_components/src/axi_lite_master.vhd b/vunit/vhdl/verification_components/src/axi_lite_master.vhd
@@ -132,9 +132,8 @@ begin
         expected_resp := pop_std_ulogic_vector(request_msg) when is_axi_lite_msg(msg_type) else axi_resp_okay;
         push(reply_queue, request_msg);
 
-        araddr <= addr_this_transaction;
-
         arvalid <= '1';
+        araddr <= addr_this_transaction;
         wait until (arvalid and arready) = '1' and rising_edge(aclk);
         arvalid <= '0';
         drive_ar_invalid;