Add VHDLStandard type annotations

vunit/builtins.py

@@ -11,7 +11,7 @@
 from os.path import join, abspath, dirname, basename
 from glob import glob
 from warnings import warn
-from vunit.vhdl_standard import VHDL
+from vunit.vhdl_standard import VHDL, VHDLStandard
 from vunit.sim_if.common import simulator_check
 
 VHDL_PATH = abspath(join(dirname(__file__), "vhdl"))
@@ -23,7 +23,7 @@ class Builtins(object):
     Manage VUnit builtins and their dependencies
     """
 
-    def __init__(self, vunit_obj, vhdl_standard, simulator_class):
+    def __init__(self, vunit_obj, vhdl_standard: VHDLStandard, simulator_class):
         self._vunit_obj = vunit_obj
         self._vunit_lib = vunit_obj.add_library("vunit_lib")
         self._vhdl_standard = vhdl_standard

vunit/project.py

@@ -13,15 +13,21 @@
 """
 from os.path import join, basename, dirname, isdir, exists
 import logging
+from typing import Optional
 from collections import OrderedDict
 from vunit.hashing import hash_string
 from vunit.dependency_graph import DependencyGraph, CircularDependencyException
 from vunit.vhdl_parser import VHDLParser
 from vunit.parsing.verilog.parser import VerilogParser
 from vunit.exceptions import CompileError
 from vunit import ostools
-from vunit.source_file import VERILOG_FILE_TYPES, VerilogSourceFile, VHDLSourceFile
-from vunit.vhdl_standard import VHDL
+from vunit.source_file import (
+    VERILOG_FILE_TYPES,
+    SourceFile,
+    VerilogSourceFile,
+    VHDLSourceFile,
+)
+from vunit.vhdl_standard import VHDL, VHDLStandard
 
 LOGGER = logging.getLogger(__name__)
 
@@ -76,7 +82,11 @@ def add_builtin_library(self, logical_name):
         self._builtin_libraries.add(logical_name)
 
     def add_library(
-        self, logical_name, directory, vhdl_standard=VHDL.STD_2008, is_external=False
+        self,
+        logical_name,
+        directory,
+        vhdl_standard: VHDLStandard = VHDL.STD_2008,
+        is_external=False,
     ):
         """
         Add library to project with logical_name located or to be located in directory
@@ -108,7 +118,7 @@ def add_source_file(  # pylint: disable=too-many-arguments
         file_type="vhdl",
         include_dirs=None,
         defines=None,
-        vhdl_standard=None,
+        vhdl_standard: Optional[VHDLStandard] = None,
         no_parse=False,
     ):
         """
@@ -124,7 +134,7 @@ def add_source_file(  # pylint: disable=too-many-arguments
 
         if file_type == "vhdl":
             assert include_dirs is None
-            source_file = VHDLSourceFile(
+            source_file: SourceFile = VHDLSourceFile(
                 file_name,
                 library,
                 vhdl_parser=self._vhdl_parser,
@@ -619,28 +629,30 @@ class Library(object):  # pylint: disable=too-many-instance-attributes
     Represents a VHDL library
     """
 
-    def __init__(self, name, directory, vhdl_standard, is_external=False):
+    def __init__(
+        self, name: str, directory: str, vhdl_standard: VHDLStandard, is_external=False
+    ):
         self.name = name
         self.directory = directory
 
         # Default VHDL standard for files added unless explicitly set per file
         self.vhdl_standard = vhdl_standard
 
-        self._source_files = {}
+        self._source_files = {}  # type: ignore
 
         # Entity objects
-        self._entities = {}
-        self._package_bodies = {}
+        self._entities = {}  # type: ignore
+        self._package_bodies = {}  # type: ignore
 
-        self.primary_design_units = {}
+        self.primary_design_units = {}  # type: ignore
 
         # Entity name to architecture design unit mapping
-        self._architectures = {}
+        self._architectures = {}  # type: ignore
 
         # Verilog specific
         # Module objects
-        self.modules = {}
-        self.verilog_packages = {}
+        self.modules = {}  # type: ignore
+        self.verilog_packages = {}  # type: ignore
 
         self._is_external = is_external
 

vunit/source_file.py

@@ -17,6 +17,7 @@
 from vunit.cached import file_content_hash
 from vunit.parsing.encodings import HDL_FILE_ENCODING
 from vunit.design_unit import DesignUnit, VHDLDesignUnit, Entity, Module
+from vunit.vhdl_standard import VHDLStandard
 
 LOGGER = logging.getLogger(__name__)
 
@@ -202,11 +203,17 @@ class VHDLSourceFile(SourceFile):
     """
 
     def __init__(  # pylint: disable=too-many-arguments
-        self, name, library, vhdl_parser, database, vhdl_standard, no_parse=False
+        self,
+        name,
+        library,
+        vhdl_parser,
+        database,
+        vhdl_standard: VHDLStandard,
+        no_parse=False,
     ):
         SourceFile.__init__(self, name, library, "vhdl")
-        self.dependencies = []
-        self.depending_components = []
+        self.dependencies = []  # type: ignore
+        self.depending_components = []  # type: ignore
         self._vhdl_standard = vhdl_standard
 
         if not no_parse:
@@ -225,7 +232,7 @@ def __init__(  # pylint: disable=too-many-arguments
             self.name, encoding=HDL_FILE_ENCODING, database=database
         )
 
-    def get_vhdl_standard(self):
+    def get_vhdl_standard(self) -> VHDLStandard:
         """
         Return the VHDL standard used to create this file
         """

vunit/ui/__init__.py

@@ -16,6 +16,7 @@
 import logging
 import json
 import os
+from typing import Optional, Set
 from os.path import exists, abspath, join, basename, normpath, dirname
 from fnmatch import fnmatch
 from ..database import PickledDataBase, DataBase
@@ -31,7 +32,7 @@
 from ..check_preprocessor import CheckPreprocessor
 from ..parsing.encodings import HDL_FILE_ENCODING
 from ..builtins import Builtins
-from ..vhdl_standard import VHDL
+from ..vhdl_standard import VHDL, VHDLStandard
 from ..test.bench_list import TestBenchList
 from ..test.report import TestReport
 from ..test.runner import TestRunner
@@ -56,7 +57,9 @@ class VUnit(  # pylint: disable=too-many-instance-attributes, too-many-public-me
     """
 
     @classmethod
-    def from_argv(cls, argv=None, compile_builtins=True, vhdl_standard=None):
+    def from_argv(
+        cls, argv=None, compile_builtins=True, vhdl_standard: Optional[str] = None
+    ):
         """
         Create VUnit instance from command line arguments.
 
@@ -80,7 +83,9 @@ def from_argv(cls, argv=None, compile_builtins=True, vhdl_standard=None):
         )
 
     @classmethod
-    def from_args(cls, args, compile_builtins=True, vhdl_standard=None):
+    def from_args(
+        cls, args, compile_builtins=True, vhdl_standard: Optional[str] = None
+    ):
         """
         Create VUnit instance from args namespace.
         Intended for users who adds custom command line options.
@@ -96,7 +101,9 @@ def from_args(cls, args, compile_builtins=True, vhdl_standard=None):
         """
         return cls(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard)
 
-    def __init__(self, args, compile_builtins=True, vhdl_standard=None):
+    def __init__(
+        self, args, compile_builtins=True, vhdl_standard: Optional[str] = None
+    ):
         self._args = args
         self._configure_logging(args.log_level)
         self._output_path = abspath(args.output_path)
@@ -117,9 +124,9 @@ def test_filter(name, attribute_names):
             return keep
 
         self._test_filter = test_filter
-        self._vhdl_standard = select_vhdl_standard(vhdl_standard)
+        self._vhdl_standard: VHDLStandard = select_vhdl_standard(vhdl_standard)
 
-        self._external_preprocessors = []
+        self._external_preprocessors = []  # type: ignore
         self._location_preprocessor = None
         self._check_preprocessor = None
 
@@ -184,7 +191,7 @@ def _configure_logging(log_level):
             filename=None, format="%(levelname)7s - %(message)s", level=level
         )
 
-    def _which_vhdl_standard(self, vhdl_standard):
+    def _which_vhdl_standard(self, vhdl_standard: Optional[str]) -> VHDLStandard:
         """
         Return default vhdl_standard if the argument is None
         The argument is a string from the user
@@ -194,7 +201,9 @@ def _which_vhdl_standard(self, vhdl_standard):
 
         return VHDL.standard(vhdl_standard)
 
-    def add_external_library(self, library_name, path, vhdl_standard=None):
+    def add_external_library(
+        self, library_name, path, vhdl_standard: Optional[str] = None
+    ):
         """
         Add an externally compiled library as a black-box
 
@@ -220,7 +229,9 @@ def add_external_library(self, library_name, path, vhdl_standard=None):
         )
         return self.library(library_name)
 
-    def add_source_files_from_csv(self, project_csv_path, vhdl_standard=None):
+    def add_source_files_from_csv(
+        self, project_csv_path, vhdl_standard: Optional[str] = None
+    ):
         """
         Add a project configuration, mapping all the libraries and files
 
@@ -233,7 +244,7 @@ def add_source_files_from_csv(self, project_csv_path, vhdl_standard=None):
         :returns: A list of files (:class `.SourceFileList`) that were added
 
         """
-        libs = set()
+        libs: Set[str] = set()
         files = SourceFileList(list())
 
         with open(project_csv_path) as csv_path_file:
@@ -258,7 +269,9 @@ def add_source_files_from_csv(self, project_csv_path, vhdl_standard=None):
                     )
         return files
 
-    def add_library(self, library_name, vhdl_standard=None, allow_duplicate=False):
+    def add_library(
+        self, library_name, vhdl_standard: Optional[str] = None, allow_duplicate=False
+    ):
         """
         Add a library managed by VUnit.
 
@@ -277,11 +290,11 @@ def add_library(self, library_name, vhdl_standard=None, allow_duplicate=False):
            library = prj.add_library("lib")
 
         """
-        vhdl_standard = self._which_vhdl_standard(vhdl_standard)
+        standard = self._which_vhdl_standard(vhdl_standard)
 
         path = join(self._simulator_output_path, "libraries", library_name)
         if not self._project.has_library(library_name):
-            self._project.add_library(library_name, abspath(path), vhdl_standard)
+            self._project.add_library(library_name, abspath(path), standard)
         elif not allow_duplicate:
             raise ValueError(
                 "Library %s already added. Use allow_duplicate to ignore this error."
@@ -500,7 +513,7 @@ def add_source_files(  # pylint: disable=too-many-arguments
         include_dirs=None,
         defines=None,
         allow_empty=False,
-        vhdl_standard=None,
+        vhdl_standard: Optional[str] = None,
         no_parse=False,
         file_type=None,
     ):
@@ -544,7 +557,7 @@ def add_source_file(  # pylint: disable=too-many-arguments
         preprocessors=None,
         include_dirs=None,
         defines=None,
-        vhdl_standard=None,
+        vhdl_standard: Optional[str] = None,
         no_parse=False,
         file_type=None,
     ):
@@ -872,7 +885,7 @@ def _create_output_path(self, clean):
         ostools.renew_path(self._preprocessed_path)
 
     @property
-    def vhdl_standard(self):
+    def vhdl_standard(self) -> str:
         return str(self._vhdl_standard)
 
     @property

vunit/ui/common.py

@@ -10,15 +10,16 @@
 
 from os import environ
 from logging import getLogger
-from ..vhdl_standard import VHDL
+from typing import Optional
+from ..vhdl_standard import VHDL, VHDLStandard
 
 
 LOGGER = getLogger(__name__)
 
 TEST_OUTPUT_PATH = "test_output"
 
 
-def select_vhdl_standard(vhdl_standard=None):
+def select_vhdl_standard(vhdl_standard: Optional[str] = None) -> VHDLStandard:
     """
     Select VHDL standard either from class initialization or according to environment variable VUNIT_VHDL_STANDARD
     """

vunit/ui/library.py

@@ -11,11 +11,12 @@
 from os.path import abspath
 from glob import glob
 from fnmatch import fnmatch
-from ..vhdl_standard import VHDL
+from typing import Optional, List
+from ..vhdl_standard import VHDL, VHDLStandard
+from ..project import Project
 from ..sim_if import is_string_not_iterable
 from ..source_file import file_type_of, FILE_TYPES, VERILOG_FILE_TYPES
 from ..builtins import add_verilog_include_dir
-
 from .common import check_not_empty
 from .source import SourceFile, SourceFileList
 from .testbench import TestBench
@@ -27,7 +28,7 @@ class Library(object):
     User interface of a library
     """
 
-    def __init__(self, library_name, parent, project, test_bench_list):
+    def __init__(self, library_name, parent, project: Project, test_bench_list):
         self._library_name = library_name
         self._parent = parent
         self._project = project
@@ -163,7 +164,7 @@ def add_source_files(  # pylint: disable=too-many-arguments
         include_dirs=None,
         defines=None,
         allow_empty=False,
-        vhdl_standard=None,
+        vhdl_standard: Optional[str] = None,
         no_parse=False,
         file_type=None,
     ):
@@ -192,7 +193,7 @@ def add_source_files(  # pylint: disable=too-many-arguments
         else:
             patterns = pattern
 
-        file_names = []
+        file_names: List[str] = []
         for pattern_instance in patterns:
             new_file_names = glob(pattern_instance)
             check_not_empty(
@@ -223,7 +224,7 @@ def add_source_file(  # pylint: disable=too-many-arguments
         preprocessors=None,
         include_dirs=None,
         defines=None,
-        vhdl_standard=None,
+        vhdl_standard: Optional[str] = None,
         no_parse=False,
         file_type=None,
     ):
@@ -357,7 +358,7 @@ def get_test_benches(self, pattern="*", allow_empty=False):
             "No test benches found within library %s" % self._library_name,
         )
 
-    def _which_vhdl_standard(self, vhdl_standard):
+    def _which_vhdl_standard(self, vhdl_standard: Optional[str]) -> VHDLStandard:
         """
         Return default vhdl_standard if the argument is None
         The argument is a string from the user