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VUnit · Mar 11, 2023 · 90fda0f · 90fda0f
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diff --git a/docs/_changes/072adda6.commit.md b/docs/_changes/072adda6.commit.md
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+ci/push: remove job win-tagged
diff --git a/docs/_changes/0848519e.commit.md b/docs/_changes/0848519e.commit.md
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+Format tests/unit/test_vhdl_parser.py to pass black
diff --git a/docs/_changes/0ea0312d.commit.md b/docs/_changes/0ea0312d.commit.md
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+Replace deprecated log level verbose with trace.
diff --git a/docs/_changes/0eed8880.commit.md b/docs/_changes/0eed8880.commit.md
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+Replace inspect method removed in Python 3.11
diff --git a/docs/_changes/1464f67e.commit.md b/docs/_changes/1464f67e.commit.md
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+Removed ambiguity in string literal.
diff --git a/docs/_changes/1adf1cfe.commit.md b/docs/_changes/1adf1cfe.commit.md
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+Remove deprecated U mode for open().
+
+U is now the default behavior and superfluous.
diff --git a/docs/_changes/1fa0f757.commit.md b/docs/_changes/1fa0f757.commit.md
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+Fix axi_lite_master wait behaviour if idle
diff --git a/docs/_changes/242e2333.commit.md b/docs/_changes/242e2333.commit.md
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+OSVVM: bump to 2022.04 (#827)
diff --git a/docs/_changes/28777b38.commit.md b/docs/_changes/28777b38.commit.md
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+add flag fail_on_non_hdl_files to vivado.py
diff --git a/docs/_changes/2896a1e3.commit.md b/docs/_changes/2896a1e3.commit.md
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+Add method to get list of libraries from VUnit object.
+
+Introduced new class LibraryList and added applicable Library methods to the class.
diff --git a/docs/_changes/2f72ad0e.commit.md b/docs/_changes/2f72ad0e.commit.md
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+Improved identity integration in logging.
diff --git a/docs/_changes/2fdbc49a.commit.md b/docs/_changes/2fdbc49a.commit.md
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+Update detection of GCC backend to match new format.
diff --git a/docs/_changes/3292c28d.commit.md b/docs/_changes/3292c28d.commit.md
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+Added missing pylint exception.
diff --git a/docs/_changes/333c465d.commit.md b/docs/_changes/333c465d.commit.md
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+Removed delta cycle race conditions. Fixes  #642.
diff --git a/docs/_changes/33dc65ab.commit.md b/docs/_changes/33dc65ab.commit.md
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+added byte enable test case
diff --git a/docs/_changes/3566d02a.commit.md b/docs/_changes/3566d02a.commit.md
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+Added get_lineage and renamed exists to has_id
diff --git a/docs/_changes/3599646a.commit.md b/docs/_changes/3599646a.commit.md
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+Add supports_vhdl_call_paths
diff --git a/docs/_changes/393c20c2.commit.md b/docs/_changes/393c20c2.commit.md
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+Update detection of LLVM backend to match new format.
diff --git a/docs/_changes/3b6e59aa.commit.md b/docs/_changes/3b6e59aa.commit.md
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+Reused name validity checking from id_pkg in logger
diff --git a/docs/_changes/3c8e9ddd.commit.md b/docs/_changes/3c8e9ddd.commit.md
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+Updated identity user guide
diff --git a/docs/_changes/4058364f.commit.md b/docs/_changes/4058364f.commit.md
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+readme: update shield syntax (badges/shields#8671)
diff --git a/docs/_changes/425e5eea.commit.md b/docs/_changes/425e5eea.commit.md
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+docs: run black
diff --git a/docs/_changes/42875fa1.commit.md b/docs/_changes/42875fa1.commit.md
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+Move identity package to data_types.
diff --git a/docs/_changes/44.changes.md b/docs/_changes/44.changes.md
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+# Add NVC simulator support
+
+I am in progress of adding support for the [NVC simulator](https://github.com/nickg/nvc). There are still some bugs and features to be fixed be before we can add support for it but the author is very cooperative and is making great progress.
+
diff --git a/docs/_changes/4a0e2583.commit.md b/docs/_changes/4a0e2583.commit.md
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+Fixed pylint warnings.
diff --git a/docs/_changes/4c062cbd.commit.md b/docs/_changes/4c062cbd.commit.md
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+Bump GitHub action versions
diff --git a/docs/_changes/4d6f3334.commit.md b/docs/_changes/4d6f3334.commit.md
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+Replaced logger internal name management with id_t from id_pkg.
diff --git a/docs/_changes/4f78fc4f.commit.md b/docs/_changes/4f78fc4f.commit.md
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+docs: add section Overview, including a diagram (#779)
diff --git a/docs/_changes/511a218f.commit.md b/docs/_changes/511a218f.commit.md
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+Added exists function and specified behavior for null_id inputs.
diff --git a/docs/_changes/5187ed27.commit.md b/docs/_changes/5187ed27.commit.md
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+Improve the tests and corrected the regex into a raw string
diff --git a/docs/_changes/55b15a68.commit.md b/docs/_changes/55b15a68.commit.md
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+Clarify that VUNIT_SIMULATOR is set to modelsim when using Questa.
+
+Closes #834
diff --git a/docs/_changes/57639004.commit.md b/docs/_changes/57639004.commit.md
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+Improved --clean help with example.example
+
+Closes #810.
diff --git a/docs/_changes/5d4fc215.commit.md b/docs/_changes/5d4fc215.commit.md
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+Add pictures for the 'allow_missing_start' of the 'check_next' procedure (see #576). Indicates in the timing diagram when the options 'allow_overlapping' and 'allow_missing_start' add no influence regarding the given example.
diff --git a/docs/_changes/602ca4d7.commit.md b/docs/_changes/602ca4d7.commit.md
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+Fixed dependencies for linting.
diff --git a/docs/_changes/619cfed7.commit.md b/docs/_changes/619cfed7.commit.md
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+Added id_pkg to handle name hierarchies programmatically.
diff --git a/docs/_changes/62654e01.commit.md b/docs/_changes/62654e01.commit.md
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+axi_stream: fix back-to-back transfer
+
+During the delta-cycle for handling of 'notify_bus_process_done', new
+message_queue items may be issued, esp. when running the "other side"
+in a "single sample while loop". Checking the queue before sleeping
+allows back-to-back reads/writes of the axi-stream.
diff --git a/docs/_changes/642.changes.md b/docs/_changes/642.changes.md
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+# vcomponents tests are failling with ModelSim
+
+When running vcomponents tests, several are failling:
+`tox -v -e py36-vcomponents-modelsim`
+
+```
+fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=0.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=8.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=0.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=0 dest_l=8 user_l=8.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=0.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=8 dest_l=0 user_l=8.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=0.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_axi_stream.id_l=8 dest_l=8 user_l=8.test back-to-back failing check                                                                         (1.0 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle                         (1.0 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle                         (1.1 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle                         (1.0 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.0,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle                         (1.0 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:1.0,transfers:64.wait until idle                         (1.0 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:1.0,read_prob:0.3,transfers:64.wait until idle                         (1.1 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:1.0,transfers:64.wait until idle                         (1.1 seconds)
+fail vunit_lib.tb_avalon_master.readdatavalid_prob:1.0,waitrequest_prob:0.7,write_prob:0.3,read_prob:0.3,transfers:64.wait until idle                         (1.0 seconds)
+=================================================================================================================================================================================
+pass 473 of 489
+fail 16 of 489
+=================================================================================================================================================================================
+Total time was 493.0 seconds
+Elapsed time was 493.9 seconds
+```
+
+```
+ # ** Note: Got mocked log item 
+#    time = 45000 ps
+#    logger = check
+#    log_level = error
+#    msg = TLAST mismatch, check non-blocking - Got 1. Expected 0.
+#    file_name:line_num = :0
+# 
+#    Time: 45 ns  Iteration: 0  Instance: /tb_axi_stream/axi_stream_slave_inst
+# ** Failure: log item mismatch:
+# 
+# Got:
+#    logger = check
+#    log_level = pass
+#    msg = Invalid strb not X
+#    file_name:line_num = :0
+# 
+# expected:
+#    logger = check
+#    log_level = error
+#    msg = TDATA mismatch, check non-blocking - Got 0000_0011 (3). Expected 0000_0110 (6).
+#    file_name:line_num = :0
+```
+
+```
+fail (P=0 S=0 F=1 T=1) vunit_lib.tb_axi_stream.id_l=0 dest_l=0 user_l=0.test back-to-back failing check (2.4 seconds)
+```
+
+Details for the failures can be found  [here](https://pastebin.com/7yQ7477p) and [there](https://pastebin.com/GSE8CbiR).
+Environment is VUnit 4.4.0 and ModelSim 10.6c.
diff --git a/docs/_changes/6705a821.commit.md b/docs/_changes/6705a821.commit.md
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+ci: add workflow_dispatch (#911)
diff --git a/docs/_changes/68cb6e85.commit.md b/docs/_changes/68cb6e85.commit.md
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+Update Sphinx configuration to support v5.0.0.
diff --git a/docs/_changes/6add51fa.commit.md b/docs/_changes/6add51fa.commit.md
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+Use the appropriate function to get the content of a JSON object
diff --git a/docs/_changes/6ec85f55.commit.md b/docs/_changes/6ec85f55.commit.md
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+pyproject: add NVC
diff --git a/docs/_changes/754.changes.md b/docs/_changes/754.changes.md
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+# Cannot use externally compiled OSVVM as external library
+
+Hi,
+I am unable to use an externally compiled version of OSVVM as an external library. This includes the base osvvm library, but also other OSVVM libraries that are not distributed with VUnit (specifically the osvvm_axi4 library).
+
+When running the run.py script it seems to successfully add the external libraries, but then errors when it comes to compile the testbench that uses the library:
+`COMP96 ERROR COMP96_0059: "Library "osvvm" not found."`
+
+This only seems to be a problem with OSVVM libraries; other external libraries work fine. This error also disappears if `vu.add_osvvm()` is used instead of trying to use the external library, but a similar error is still present for other OSVVM external libraries:
+`COMP96 ERROR COMP96_0059: "Library "osvvm_axi4" not found."`
+Including both `add_osvvm()` and the external library predictably results in a name clash when run.py is run:
+`ValueError: Library osvvm already exists`
+
+I am using:
+- python 3.6.9
+- vunit-hdl 4.5.0
+- Riviera-PRO 2020.10
diff --git a/docs/_changes/757.changes.md b/docs/_changes/757.changes.md
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+# add 'compile_builtins' deprecation warning
+
+This PR lays the ground for deprecating `compile_builtins` and `vunit.verilog` in upcoming releases (not the next one). As discussed in #559, `add_builtins` is to be split into `add_vhdl_builtins` and `add_verilog_builtins`. In the future, users will need to use them explicitly (as it is required for `add_osvvm` or `add_verification_components`).
+
+In this PR, `compile_builtins` is NOT deprecated yet. A warning is added, which will be shown to all the users which are currently using it. Since it is enabled by default, it will be shown for most of the current users of VUnit. The recommendation is that they can use `compile_builtins=False` and `VU.add_vhdl_builtins` now, or wait until the deprecation.
+
+This PR does include a breaking change in the public API, since `add_builtins` is renamed to `add_vhdl_builtins`. That is to avoid the warning recommending the users a function that is to be removed (`add_builtins`). However, since the vast majority of VUnit users should not even be aware that `add_builtins` exists, this change should not be disruptive.
+
+BTW, for some reason `add_builtins` was not shown in the documentation. I don't remember whether it was hidden on purpose (because of being redundant to `compile_builtins`) or because it crashed Sphinx. Anyway, I fixed the docstring and, since it is split, the documentation now includes both `add_verilog_builtins` and `add_vhdl_builtins`.
diff --git a/docs/_changes/758594b3.commit.md b/docs/_changes/758594b3.commit.md
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+readme: add banner; update shields/badges
diff --git a/docs/_changes/758b9e47.commit.md b/docs/_changes/758b9e47.commit.md
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+JSON-for-VHDL: bump to 95e848b8 (Paebbels/JSON-for-VHDL#14)
diff --git a/docs/_changes/762.changes.md b/docs/_changes/762.changes.md
@@ -0,0 +1,3 @@
+# docs: add subdir 'logo'; add banner
+
+In this PR, the SVG sources of the logo are moved to subdir 'logo', so that `docs/_static` contains the sources to be used in the Sphinx site only. At the same time, since I got to install the correct font, `logo/banners.svg` is added, which includes multiple possible banners. One of them is used in the README. By the way, the icons in the shields/badges are updated. See https://github.com/dbhi/vunit/tree/docs-logo.
diff --git a/docs/_changes/768.changes.md b/docs/_changes/768.changes.md
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+# Riviera fails to compile OSVVM 2021.09
+
+Starting with VUnit 4.6.0 I get an error when compiling OSVVM with Riviera (2020.10 and 2019.04):
+
+```=== Command output: ===
+COMP96 WARNING COMP96_0048: "This function may complete without return statement." "/home/domain/crdavis/virtualenv/msry_env/lib/python3.7/site-packages/vunit/vhdl/osvvm/ScoreboardPkg_slv_c.vhd" 1795 5
+COMP96 WARNING COMP96_0048: "This function may complete without return statement." "/home/domain/crdavis/virtualenv/msry_env/lib/python3.7/site-packages/vunit/vhdl/osvvm/ScoreboardPkg_slv_c.vhd" 2225 5
+COMP96 ERROR COMP96_0106: "Returned value type does not match the type declared in function declaration." "/home/domain/crdavis/virtualenv/msry_env/lib/python3.7/site-packages/vunit/vhdl/osvvm/ScoreboardPkg_slv_c.vhd" 2619 12
+COMP96 ERROR COMP96_0106: "Returned value type does not match the type declared in function declaration." "/home/domain/crdavis/virtualenv/msry_env/lib/python3.7/site-packages/vunit/vhdl/osvvm/ScoreboardPkg_slv_c.vhd" 2627 12
+COMP96 Compile failure 2 Errors 2 Warnings  Analysis time :  30.0 [ms]
+```
+
+It looks like this is a non-generic package included for compatability with Cadence. [OSVVM](https://github.com/OSVVM/OSVVM/blob/71faba779aebe79d3a48ce0abc0a9adc272f99ae/osvvm.pro) has the following in their build script:
+
+```
+if {$::osvvm::ToolVendor ne "Cadence"}  {
+  analyze ScoreboardGenericPkg.vhd
+  analyze ScoreboardPkg_slv.vhd
+  analyze ScoreboardPkg_int.vhd
+} else {
+  analyze ScoreboardPkg_slv_c.vhd
+  analyze ScoreboardPkg_int_c.vhd
+}
+```
+
+Which makes me think something similar is needed in [builtins._add_osvvm](https://github.com/VUnit/vunit/blob/master/vunit/builtins.py)
diff --git a/docs/_changes/769.changes.md b/docs/_changes/769.changes.md
@@ -0,0 +1,3 @@
+# Skip non-generic osvvm packages when the simulator supports generics
+
+Fixes #768.
diff --git a/docs/_changes/771.changes.md b/docs/_changes/771.changes.md
@@ -0,0 +1,11 @@
+# builtins: skip addition of builtins if the library is added previously
+
+As discussed in #767, this PR modifies the functions for adding the built OSVVM and JSON-for-VHDL.  Currently, a try...except block is used:
+
+https://github.com/VUnit/vunit/blob/7879504ba6a97be82137199e8819f770e4017681/vunit/builtins.py#L139-L142
+
+That approach has two main caveats. On the one hand, the `try` statement is not case sensitive. Hence, if a library named `OSVVM` exists, it does not get it when asking for `osvvm`. That falls back to the exception, which crashes because adding a library is case insensitive. If no crash is produced, additional sources are added to the existing library.
+
+In this PR, `_add_library_if_not_exist` is added, which lowercases library names to check if it exists. Furthermore, if the library exists already, adding builtins is skipped, instead of mixing the content.
+
+I didn't find any function in the API for retrieving the names of the libraries declared already. Hence, I used `[library.lower() for library in self._vunit_obj._project._libraries]`. However, we might want to add it in the project class.
diff --git a/docs/_changes/773.changes.md b/docs/_changes/773.changes.md
@@ -0,0 +1,46 @@
+# Preprocessor issue higher case
+
+I have tried the feature of adding line_num and file_name to a convenience procudure, like describes in the documentation
+
+### Documentation:
+
+With earlier VHDL standard you can add the line_num and file_name parameters to the end of the parameter list for the convenience procedure
+
+procedure my_convenience_procedure(
+  <my parameters>
+  line_num : natural := 0;
+  file_name : string := "") is
+begin
+  <some code>
+  info("Some message", line_num => line_num, file_name => file_name);
+  <some code>
+end procedure my_convenience_procedure;
+and then let the location preprocessor know about the added procedure
+
+ui = VUnit.from_argv()
+ui.enable_location_preprocessing(additional_subprograms=['my_convenience_procedure'])
+
+### BUG:
+
+It was really frustatric sine it did not work. I could see that the preprocessor did some wired stuff. It added addtional ines to the code at wrong position.
+
+	PROCEDURE my_convenience_procedure (
+		SIGNAL test : OUT STD_LOGIC;
+		line_num    : NATURAL := 0;
+		file_name   : STRING, line_num => 57, file_name => "Testbench.vhd") IS    ==>>> THIS LINE IS WRONG
+	begin
+		test <= '1';
+		info("Some message", line_num => line_num, file_name => file_name);
+		test <= '0';
+	END PROCEDURE;
+
+
+### SOLUTION: 
+Then I tried to write PROCEDURE in lower case (actually my VHDL-formatter does this) 
+And suddenly everything works well. 
+
+To there is an issue with this preprocessor.
+
+
+
+
diff --git a/docs/_changes/774.changes.md b/docs/_changes/774.changes.md
@@ -0,0 +1,3 @@
+# Fix location preprocessor casing bug. Related to #773.
+
+
diff --git a/docs/_changes/778.changes.md b/docs/_changes/778.changes.md
@@ -0,0 +1,3 @@
+# ui: update docstrings to explain the deprecation of 'compile_builtins'; update refs
+
+In the context of #777, this PR updates the docstrings and the CLI note with regard to the deprecation of `compile_builtins`.
diff --git a/docs/_changes/779.changes.md b/docs/_changes/779.changes.md
@@ -0,0 +1,6 @@
+# docs: add section Overview, including a diagram
+
+This PR adds subsection 'Overview' to section 'What is VUnit?'. A diagram based on [umarcor.github.io/osvb/intro](https://umarcor.github.io/osvb/intro) is included.
+
+![image](https://user-images.githubusercontent.com/38422348/141665061-3ab290fc-6b5c-4653-899c-3f729d87dbb5.png)
+
diff --git a/docs/_changes/77cc839d.commit.md b/docs/_changes/77cc839d.commit.md
@@ -0,0 +1,3 @@
+axi_stream_slave: fix memory leak
+
+The pop'ed message must be deleted after being parsed.
diff --git a/docs/_changes/780.changes.md b/docs/_changes/780.changes.md
@@ -0,0 +1,3 @@
+# OSVVM: bump to 2021.10
+
+OSVVM 2021.10 was released some hours ago. This PR bumps the submodule in VUnit.
diff --git a/docs/_changes/781.changes.md b/docs/_changes/781.changes.md
@@ -0,0 +1,6 @@
+# Added support for detecting and failing on ambiguous direct entity instantiations.
+
+This happens when an entity has several architectures but the architecture
+is not specified in the instantiation. VHDL allows this and selects the
+last successfully compiled architecture. This can never be what the
+designer intended since she cannot fully control compile order.
diff --git a/docs/_changes/782.changes.md b/docs/_changes/782.changes.md
@@ -0,0 +1,25 @@
+# Vivado compile order scanning fails with .coe or .mif dependencies
+
+vivado.py function _read_compile_order() used by add_vivado_ip() fails with assertion when compile_order.txt contains references to files that are not VHDL or Verilog. However, some Vivado IP include .coe or .mif memory initialisation files. 
+
+Ideally, these ressource files should get copied (or symlinked) by VUnit to the simulator_output_path, so that they are available for the simulator. At the least, the assertion failure at line vivado.py:93 should  be reduced to a warning (and the line ignored), so that the function does not fail.
+
+My dirty workaround right now is changing the assert to a continue and using a pre_config to copy the ressource later.
+
+vivado.py:93
+```
+if file_type not in ("Verilog", "VHDL", "Verilog Header"):
+    print("Warning: compile_order.txt entry ignored: %s" % line)
+    continue
+```
+
+run.py
+```
+def pre_config (output_path, simulator_output_path):
+    shutil.copy(root + "hdl/ip/lutram/lutram.mif", simulator_output_path)
+    return True
+
+for tb in lib.get_test_benches():
+    tb.set_pre_config(pre_config)
+```
+
diff --git a/docs/_changes/786.changes.md b/docs/_changes/786.changes.md
@@ -0,0 +1,5 @@
+# add flag fail_on_non_hdl_files to vivado.py
+
+Fix https://github.com/VUnit/vunit/issues/782 as suggested by @LarsAsplund 
+
+
diff --git a/docs/_changes/789.changes.md b/docs/_changes/789.changes.md
@@ -0,0 +1,3 @@
+# update license headers to 2022
+
+This is a regular bump of the license headers and the corresponding checks.
diff --git a/docs/_changes/78ef245c.commit.md b/docs/_changes/78ef245c.commit.md
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+Updated rivierapro.py as discussed in pull request #621
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+# OSVVM: bump to 2021.12
+
+OSVVM 2021.12 was released some days ago. This PR bumps the submodule in VUnit.
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		Format tests/unit/test_vhdl_parser.py to pass black
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		Replace deprecated log level verbose with trace.
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		Remove deprecated U mode for open().

		U is now the default behavior and superfluous.
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		Add method to get list of libraries from VUnit object.

		Introduced new class LibraryList and added applicable Library methods to the class.
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		Update detection of GCC backend to match new format.
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		Removed delta cycle race conditions. Fixes #642.
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		Update detection of LLVM backend to match new format.
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		Reused name validity checking from id_pkg in logger
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		readme: update shield syntax (badges/shields#8671)
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		# Add NVC simulator support

		I am in progress of adding support for the [NVC simulator](https://github.com/nickg/nvc). There are still some bugs and features to be fixed be before we can add support for it but the author is very cooperative and is making great progress.