Added support for automatic discovery of testbench VHDL configurations.

tests/acceptance/artificial/vhdl/arch1.vhd

@@ -0,0 +1,10 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
+-- You can obtain one at http://mozilla.org/MPL/2.0/.
+--
+-- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
+
+architecture arch1 of ent is
+begin
+  arch <= "arch1";
+end;

tests/acceptance/artificial/vhdl/cfg1.vhd

@@ -4,11 +4,6 @@
 --
 -- Copyright (c) 2014-2023, Lars Asplund lars.anders.asplund@gmail.com
 
-architecture arch1 of ent is
-begin
-  arch <= "arch1";
-end;
-
 configuration cfg1 of tb_with_vhdl_configuration is
   for tb
     for ent_inst : ent

tests/acceptance/artificial/vhdl/run.py

@@ -94,27 +94,10 @@ def configure_tb_assert_stop_level(ui):
             test.set_sim_option("vhdl_assert_stop_level", vhdl_assert_stop_level)
 
 
-def configure_tb_with_vhdl_configuration(ui):
-    def make_post_check(expected_arch):
-        def post_check(output_path):
-            arch = (Path(output_path) / "result.txt").read_text()
-            if arch[:-1] != expected_arch:
-                raise RuntimeError(f"Error! Got {arch[: -1]}, expected {expected_arch}")
-
-            return True
-
-        return post_check
-
-    tb = ui.library("lib").entity("tb_with_vhdl_configuration")
-    tb.add_config(name="cfg1", post_check=make_post_check("arch1"), vhdl_configuration_name="cfg1")
-    tb.add_config(name="cfg2", post_check=make_post_check("arch2"), vhdl_configuration_name="cfg2")
-
-
 configure_tb_with_generic_config()
 configure_tb_same_sim_all_pass(vu)
 configure_tb_set_generic(vu)
 configure_tb_assert_stop_level(vu)
-configure_tb_with_vhdl_configuration(vu)
 lib.entity("tb_no_generic_override").set_generic("g_val", False)
 lib.entity("tb_ieee_warning").test("pass").set_sim_option("disable_ieee_warnings", True)
 lib.entity("tb_other_file_tests").scan_tests_from_file(str(root / "other_file_tests.vhd"))

vunit/design_unit.py

@@ -41,6 +41,10 @@ def is_entity(self):
     def is_module(self):
         return False
 
+    @property
+    def is_vhdl_configuration(self):
+        return False
+
 
 class VHDLDesignUnit(DesignUnit):
     """
@@ -96,6 +100,22 @@ def is_entity(self):
         return True
 
 
+class VHDLConfiguration(VHDLDesignUnit):
+    "Represents a VHDL configuration."
+
+    def __init__(self, name, source_file, entity_name):
+        VHDLDesignUnit.__init__(self, name, source_file, "configuration", True)
+        self._entity_name = entity_name
+
+    @property
+    def entity_name(self):
+        return self._entity_name
+
+    @property
+    def is_vhdl_configuration(self):
+        return True
+
+
 class Module(DesignUnit):
     """
     Represents a Verilog Module

vunit/source_file.py

@@ -17,7 +17,7 @@
 from vunit.vhdl_parser import VHDLReference
 from vunit.cached import file_content_hash
 from vunit.parsing.encodings import HDL_FILE_ENCODING
-from vunit.design_unit import DesignUnit, VHDLDesignUnit, Entity, Module
+from vunit.design_unit import DesignUnit, VHDLDesignUnit, Entity, Module, VHDLConfiguration
 from vunit.vhdl_standard import VHDLStandard
 from vunit.library import Library
 
@@ -317,7 +317,7 @@ def _find_design_units(self, design_file):
             )
 
         for configuration in design_file.configurations:
-            result.append(VHDLDesignUnit(configuration.identifier, self, "configuration"))
+            result.append(VHDLConfiguration(configuration.identifier, self, configuration.entity))
 
         for body in design_file.package_bodies:
             result.append(VHDLDesignUnit(body.identifier, self, "package body", False, body.identifier))

vunit/test/bench_list.py

@@ -25,6 +25,7 @@ class TestBenchList(object):
     def __init__(self, database=None):
         self._libraries = OrderedDict()
         self._database = database
+        self._vhdl_configurations = {}
 
     def add_from_source_file(self, source_file):
         """
@@ -33,8 +34,25 @@ def add_from_source_file(self, source_file):
         for design_unit in source_file.design_units:
             if design_unit.is_entity or design_unit.is_module:
                 if tb_filter is None or tb_filter(design_unit):
-                    if design_unit.is_module or design_unit.is_entity:
-                        self._add_test_bench(TestBench(design_unit, self._database))
+                    test_bench = TestBench(design_unit, self._database)
+                    self._add_test_bench(test_bench)
+                    if design_unit.is_entity:
+                        if design_unit.name not in self._vhdl_configurations:
+                            self._vhdl_configurations[design_unit.name] = {"test_bench": None, "configurations": []}
+
+                        self._vhdl_configurations[design_unit.name]["test_bench"] = test_bench
+                        for configuration in self._vhdl_configurations[design_unit.name]["configurations"]:
+                            test_bench.add_config(name=configuration, vhdl_configuration_name=configuration)
+
+            if design_unit.is_vhdl_configuration:
+                if design_unit.entity_name not in self._vhdl_configurations:
+                    self._vhdl_configurations[design_unit.entity_name] = {"test_bench": None, "configurations": []}
+
+                self._vhdl_configurations[design_unit.entity_name]["configurations"].append(design_unit.name)
+                if self._vhdl_configurations[design_unit.entity_name]["test_bench"]:
+                    self._vhdl_configurations[design_unit.entity_name]["test_bench"].add_config(
+                        name=design_unit.name, vhdl_configuration_name=design_unit.name
+                    )
 
     def _add_test_bench(self, test_bench):
         """

vunit/ui/testbench.py

@@ -130,7 +130,6 @@ def add_config(  # pylint: disable=too-many-arguments
         post_check=None,
         sim_options=None,
         attributes=None,
-        vhdl_configuration_name=None,
     ):
         """
         Add a configuration of this test bench or to all test cases within it by copying the default configuration.
@@ -182,7 +181,6 @@ def add_config(  # pylint: disable=too-many-arguments
             post_check=post_check,
             sim_options=sim_options,
             attributes=attributes,
-            vhdl_configuration_name=vhdl_configuration_name,
         )
 
     def test(self, name):

vunit/vhdl_parser.py

@@ -125,7 +125,7 @@ def find(cls, code):
 
 class VHDLConfiguration(object):
     """
-    A configuratio declaration
+    A configuration declaration
     """
 
     def __init__(self, identifier, entity):