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mixed mode simulations #97
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We do have a concept for per file based compilation options. See So you are running SystemVerilog testbenches through VUnit? You must like to be on the bleeding edge. SV support is not something we even officially have yet and the hidden support we do have is not complete and we do not promise that it will be stable. We have the ambition to make VUnit work just as nice with SV though. |
@kraigher funny enough - have just made the same mod - having discovered the set_compile_option! Am also happy to provide feedback through using it with systemverilog benches. |
Added |
That's great. I've noticed that the dependency checking has some issues as well - i.e. if a verilog file requires a VHDL package... I'm looking into it now, but is this something that you already have some ideas on? |
There is no dependency checking between VHDL and Verilog at the moment. |
Sure, I can do that - no problem. |
@swattor I have added a way to specify manual dependencies. |
I am trying to run a mixed-mode (SV and VHDL) simulation on modelsim through vunit.
I have certain VHDL packages that need to be compiled with the -mixedsvvh flag to allow systemverilog testbench to look at contents - but there doesn't appear to be an easy way of adding a "per file" compilation option.
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