Vhdl 2019 updates

tests/unit/test_rivierapro_interface.py

@@ -27,7 +27,10 @@ class TestRivieraProInterface(unittest.TestCase):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_vhdl_2019(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_vhdl_2019(self, _find_prefix, process, check_output):
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
         project.add_library("lib", "lib_path")
@@ -52,7 +55,7 @@ def test_compile_project_vhdl_2019(self, process, check_output):
                 "-quiet",
                 "-j",
                 self.output_path,
-                "-2018",
+                "-2019",
                 "-work",
                 "lib",
                 "file.vhd",
@@ -62,7 +65,10 @@ def test_compile_project_vhdl_2019(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_vhdl_2008(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_vhdl_2008(self, _find_prefix, process, check_output):
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
         project.add_library("lib", "lib_path")
@@ -97,7 +103,10 @@ def test_compile_project_vhdl_2008(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_vhdl_2002(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_vhdl_2002(self, _find_prefix, process, check_output):
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
         project.add_library("lib", "lib_path")
@@ -132,7 +141,10 @@ def test_compile_project_vhdl_2002(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_vhdl_93(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_vhdl_93(self, _find_prefix, process, check_output):
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
         project.add_library("lib", "lib_path")
@@ -167,7 +179,12 @@ def test_compile_project_vhdl_93(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_vhdl_extra_flags(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_vhdl_extra_flags(
+        self, _find_prefix, process, check_output
+    ):
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
         project.add_library("lib", "lib_path")
@@ -203,7 +220,10 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_verilog(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_verilog(self, _find_prefix, process, check_output):
         library_cfg = str(Path(self.output_path) / "library.cfg")
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -238,7 +258,10 @@ def test_compile_project_verilog(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_system_verilog(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_system_verilog(self, _find_prefix, process, check_output):
         library_cfg = str(Path(self.output_path) / "library.cfg")
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -274,7 +297,12 @@ def test_compile_project_system_verilog(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_verilog_extra_flags(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_verilog_extra_flags(
+        self, _find_prefix, process, check_output
+    ):
         library_cfg = str(Path(self.output_path) / "library.cfg")
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -312,7 +340,10 @@ def test_compile_project_verilog_extra_flags(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_verilog_include(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_verilog_include(self, _find_prefix, process, check_output):
         library_cfg = str(Path(self.output_path) / "library.cfg")
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()
@@ -350,7 +381,10 @@ def test_compile_project_verilog_include(self, process, check_output):
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
     @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True)
-    def test_compile_project_verilog_define(self, process, check_output):
+    @mock.patch(
+        "vunit.sim_if.rivierapro.RivieraProInterface.find_prefix", return_value="prefix"
+    )
+    def test_compile_project_verilog_define(self, _find_prefix, process, check_output):
         library_cfg = str(Path(self.output_path) / "library.cfg")
         simif = RivieraProInterface(prefix="prefix", output_path=self.output_path)
         project = Project()

vunit/sim_if/rivierapro.py

@@ -71,19 +71,26 @@ def no_avhdl(path):
         return cls.find_toolchain(["vsim", "vsimsa"], constraints=[no_avhdl])
 
     @classmethod
-    def get_osvvm_coverage_api(cls):
+    def _get_version(cls):
         """
-        Returns simulator name when OSVVM coverage API is supported, None otherwise.
+        Return a VersionConsumer object containing the simulator version.
         """
         proc = Process(
             [str(Path(cls.find_prefix()) / "vcom"), "-version"], env=cls.get_env()
         )
         consumer = VersionConsumer()
         proc.consume_output(consumer)
-        if consumer.year is not None:
-            if (consumer.year == 2016 and consumer.month >= 10) or (
-                consumer.year > 2016
-            ):
+
+        return consumer
+
+    @classmethod
+    def get_osvvm_coverage_api(cls):
+        """
+        Returns simulator name when OSVVM coverage API is supported, None otherwise.
+        """
+        version = cls._get_version()
+        if version.year is not None:
+            if (version.year == 2016 and version.month >= 10) or (version.year > 2016):
                 return cls.name
 
         return None
@@ -113,6 +120,7 @@ def __init__(self, prefix, output_path, persistent=False, gui=False):
         self._create_library_cfg()
         self._libraries = []
         self._coverage_files = set()
+        self._version = self._get_version()
 
     def add_simulator_specific(self, project):
         """
@@ -147,13 +155,19 @@ def compile_source_file_command(self, source_file):
         LOGGER.error("Unknown file type: %s", source_file.file_type)
         raise CompileError
 
-    @staticmethod
-    def _std_str(vhdl_standard):
+    def _std_str(self, vhdl_standard):
         """
         Convert standard to format of Riviera-PRO command line flag
         """
         if vhdl_standard == VHDL.STD_2019:
-            return "-2018"
+            if self._version.year is not None:
+                if (self._version.year == 2020 and self._version.month < 4) or (
+                    self._version.year < 2020
+                ):
+                    return "-2018"
+
+            return "-2019"
+
         return "-%s" % vhdl_standard
 
     def compile_vhdl_file_command(self, source_file):

vunit/vhdl/com/src/com_debug_codec_builder.vhd

@@ -205,7 +205,7 @@ package body com_debug_codec_builder_pkg is
       return;
     end if;
 
-    elements      := new line_vector(0 to max_num_of_elements - 1);
+    elements      := new work.string_ops.line_vector(0 to max_num_of_elements - 1);
     element_start := grp'left + 1;
     for i in grp'left + 1 to grp'right loop
       if length = max_num_of_elements then

vunit/vhdl/path/src/path.vhd

@@ -37,7 +37,7 @@ package body path is
     constant p9 : string := "";
     constant p10 : string := "")
     return string is
-    variable inputs : line_vector(1 to 10);
+    variable inputs : work.string_ops.line_vector(1 to 10);
     variable result : line;
   begin
     write(inputs(1), p1);