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fix broken msg passing in wishbone master for (fix #692) #693
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Original file line number | Diff line number | Diff line change |
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@@ -22,7 +22,7 @@ def encode(tb_cfg): | |
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def gen_wb_tests(obj, *args): | ||
for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob in product(*args): | ||
for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob, slave_inst in product(*args): | ||
tb_cfg = dict( | ||
dat_width=dat_width, | ||
# TODO remove fixed addr | ||
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@@ -31,6 +31,7 @@ def gen_wb_tests(obj, *args): | |
ack_prob=ack_prob, | ||
stall_prob=stall_prob, | ||
num_cycles=num_cycles, | ||
slave_inst=slave_inst | ||
) | ||
config_name = encode(tb_cfg) | ||
obj.add_config(name=config_name, generics=dict(encoded_tb_cfg=encode(tb_cfg))) | ||
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@@ -86,13 +87,17 @@ def gen_avalon_master_tests(obj, *args): | |
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for test in TB_WISHBONE_SLAVE.get_tests(): | ||
# TODO strobe_prob not implemented in slave tb | ||
gen_wb_tests(test, [8, 32], [1, 64], [1.0], [0.3, 1.0], [0.4, 0.0]) | ||
gen_wb_tests(test, [8, 32], [1, 64], [1.0], [0.3, 1.0], [0.4, 0.0], [True, ]) | ||
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TB_WISHBONE_MASTER = LIB.test_bench("tb_wishbone_master") | ||
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for test in TB_WISHBONE_MASTER.get_tests(): | ||
gen_wb_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.3, 1.0], [0.4, 0.0]) | ||
if test.name == "slave comb ack": | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I'm not sure to understand this. Why is the combinatorial version tested with one set of params but the other one is tested with two? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. slave comb ack test case doesn't need/cannot have random stimulus |
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gen_wb_tests(test, [32], [64], [1.0], [1.0], [0.0], [False, ]) | ||
else: | ||
gen_wb_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.3, 1.0], [0.4, 0.0], [True, ]) | ||
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TB_AXI_STREAM = LIB.test_bench("tb_axi_stream") | ||
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Original file line number | Diff line number | Diff line change |
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@@ -34,6 +34,7 @@ architecture a of tb_wishbone_master is | |
strobe_prob : real; | ||
ack_prob : real; | ||
stall_prob : real; | ||
slave_inst : boolean; | ||
end record tb_cfg_t; | ||
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impure function decode(encoded_tb_cfg : string) return tb_cfg_t is | ||
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@@ -43,7 +44,8 @@ architecture a of tb_wishbone_master is | |
num_cycles => positive'value(get(encoded_tb_cfg, "num_cycles")), | ||
strobe_prob => real'value(get(encoded_tb_cfg, "strobe_prob")), | ||
ack_prob => real'value(get(encoded_tb_cfg, "ack_prob")), | ||
stall_prob => real'value(get(encoded_tb_cfg, "stall_prob"))); | ||
stall_prob => real'value(get(encoded_tb_cfg, "stall_prob")), | ||
slave_inst => boolean'value(get(encoded_tb_cfg, "slave_inst"))); | ||
end function decode; | ||
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constant tb_cfg : tb_cfg_t := decode(encoded_tb_cfg); | ||
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@@ -156,6 +158,11 @@ begin | |
wait for 20 ns; | ||
end loop; | ||
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elsif run("slave comb ack") then | ||
write_bus(net, bus_handle, 0, value); | ||
wait until ack = '1' and rising_edge(clk); | ||
wait for 20 ns; | ||
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end if; | ||
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info(tb_logger, "Done, quit..."); | ||
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@@ -182,22 +189,34 @@ begin | |
ack => ack | ||
); | ||
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dut_slave : entity work.wishbone_slave | ||
generic map ( | ||
wishbone_slave => wishbone_slave | ||
) | ||
port map ( | ||
clk => clk, | ||
adr => adr, | ||
dat_i => dat_o, | ||
dat_o => dat_i, | ||
sel => sel, | ||
cyc => cyc, | ||
stb => stb, | ||
we => we, | ||
stall => stall, | ||
ack => ack | ||
); | ||
slave_gen : if tb_cfg.slave_inst generate | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Would it make sense for There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. as described in first comment IMHO: no, it would not |
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dut_slave : entity work.wishbone_slave | ||
generic map ( | ||
wishbone_slave => wishbone_slave | ||
) | ||
port map ( | ||
clk => clk, | ||
adr => adr, | ||
dat_i => dat_o, | ||
dat_o => dat_i, | ||
sel => sel, | ||
cyc => cyc, | ||
stb => stb, | ||
we => we, | ||
stall => stall, | ||
ack => ack | ||
); | ||
else generate | ||
signal wr_r : std_ulogic; | ||
begin | ||
proc : process(clk) is begin | ||
if rising_edge(clk) then | ||
wr_r <= we and cyc and stb; | ||
end if; | ||
end process; | ||
ack <= wr_r and not stall and cyc; | ||
stall <= not wr_r; | ||
end generate; | ||
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clk <= not clk after 5 ns; | ||
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I would use
slave_comb
instead ofslave_inst
, since my understanding is that the difference between the two cases is whether the slave is combinatorial or registered.There was a problem hiding this comment.
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The idea is to have possibility to skip wb slave VC instantiation and drive wishbone slave signals directly. It makes possible to test various corner cases - like here when specific set of acknowledge logic lead to crash on modelsim, but not ghdl. I thinks it's not feasible to add this corner cases reproducers to wishbone slave as it will obfuscate code. This is all about wb master VC bug.