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Minimize imports in an effort to lower simulation setup time #992
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I will accept the PR when it is green |
These changes represent a 21% reduction of execution time for the 460 test cases in hdl-modules repo: https://github.com/hdl-modules/hdl-modules For some small testbenches, the reduction is as much as 42%. Note that this repo contains only small to medium sized testbenches (1-10 seconds, with most around 1-4 seconds). This is all using the GHDL simulator with GCC backend on Linux. With ModelSim Intel FPGA starter edition 2020.1, the reductions is negligible (1-2%). This change: 1. Stop using "context" in all VUnit packages. In most packages, importing with context includes a lot more than what is actually used. 2. Stop using "use work.x_pkg.all" in cases where only 1-3 things are used from the package. Instead, one explicit "use" clause for the things that are actually used. * Not done for the most common packages (run_pkg, check_pkg, logger_pkg). * Not done for includes from very small packages. 3. For packages that have head and body in different files, move all imports to the head file. As they were, split between the files, there was a lot of overlap of imports, and it what hard to get an overview of what is actually imported and what is actually used. The first point represents roughly 80% of the performance gain. Note that in order to reach the performance gains listed above, the corresponding changes have to be made to all testbenches and simulation code in the user repo also. If the testbench includes "vunit_context", "com_context" etc, the performance gains will not be realized since everything will be imported anyway.
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Hello Lars!
Thank you! |
I have pushed a fix so that it is now green! |
See #997. |
These changes represent a 21% reduction of execution time for the 460 test cases in hdl-modules repo: https://github.com/hdl-modules/hdl-modules For some small testbenches, the reduction is as much as 42%. Note that this repo contains only small to medium sized testbenches (1-10 seconds, with most around 1-4 seconds).
This is all using the GHDL simulator with GCC backend on Linux. With ModelSim Intel FPGA starter edition 2020.1, the reductions is negligible (1-2%).
This change:
Stop using "context" in all VUnit packages. In most packages, importing with context includes a lot more than what is actually used.
Stop using "use work.x_pkg.all" in cases where only 1-3 things are used from the package. Instead, one explicit "use" clause for the things that are actually used.
Not done for the most common packages (run_pkg, check_pkg, logger_pkg).
Not done for includes from very small packages.
For packages that have head and body in different files, move all imports to the head file. As they were, split between the files, there was a lot of overlap of imports, and it what hard to get an overview of what is actually imported and what is actually used.
The first point represents roughly 80% of the performance gain.
Note that in order to reach the performance gains listed above, the corresponding changes have to be made to all testbenches and simulation code in the user repo also. If the testbench includes "vunit_context", "com_context" etc, the performance gains will not be realized since everything will be imported anyway.