Systemverilog Template

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

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• Systemverilog Template
  • To-Do
  • Before to use
    • Archlinux
    • Ubuntu
    • Last review
  • How to use it?
    • Quick use
    • Make targets
  • References

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To-Do

1. Improve documentation.
   • Explain how to create you own project.
2. Improve quartus-tools for synthesize.
   • Review quartus_map flags & document it.
   • Review global-assigments
   • Create qsf file for synthesis.
   • Complete quartus assignments descriptions.
   • Modified Makefile to use quartus-pgm tool (load the design on the board).
3. Complement the information and use of yosys.
4. Integrate Xilinx tools (on-hold)

Before to use

First you be sure that you have installed the following dependencies:

• Verilator
• GTKWave
• Quartus Prime Lite
• Yosys
• GNU Make
• Clang
• Any text editor of your choice

Note

intercept-build is part of the scan-build toolset from Clang. This tool is to create compile_commands.json that lists the exact compiler commands used to compile each source file in a project, helping tools like code editors and analyzers understand the build process.

Archlinux

On Archlinux you can install dependencies using a package manager as paru, yay or pamac. For the last version this template all dependencies have been installed using paru:

paru -S varilator gtkwave quartus-free yosys clang make arrow-usb-blaster

Ubuntu

Install dependencies using from the software sources or the software center.

sudo apt-get install verilator gtkwave clang yosys build-essential

For install quartus-prime you need to download the package from quartus for linux and install compile it

Tip

Sometimes verilator does not work properly, for solve this try to reinstall package, to be sure that verilator is working as expected run verilator --help on command line and compare the output with verilator output

Last review

The most recent revision of this project was completed using the following tools and their respective versions:

• Linux Operating System: Manjaro Linux x86_64 kernel: 6.6.52-1-MANJARO
• Verilator: Version 5.028
• GTKWave : Version v3.3.120
• Quartus Prime Lite : Version 23.1
• Yosys : Version 0.43
• GNU Make : Version 4.4.1
• Clang : Version 18.1.8
• The text editor : Neovim v0.10.1

How to use it?

Quick use

1. Verilate your project: make all or make
2. Build and run the simulation: make run
3. Once that you confirm the simulation works as you expected synthesize you project: make qrtl

Make targets

The Makefile includes the following targets:

• Main targets

  • make: Check for errors in the codes, and start the "verilating" process as well as look for errors in the test bench."
  • make run: Creates the executable, runs the simulation and displays the generated waves in GTKWave."
  • make qrtl: Do Analysis and Synthesis and open the RTLViewer with Intel tools."
  • make qfull: Full compilation & analysis with Intel® tools"
  • make view: Open RTLViewer by Intel® to view the schematic diagram."
  • make ys: Create simple RTL deagram with Yosys tool."
  • make clean: Clean the project."
  • make help: Show a short description of the commands "

• Intel® Tools targets

  • make synth: Synthesis and analysis with Intel® tools."
  • make fit: Place & Route with Intel® tools."
  • make qasm: Generate Programming Fileswith Intel® tools."
  • make qsta: Timing analysys with Intel® tools."
  • make qeda: Write EDA netlist with Intel® tools."
  • make net: Generate Netlist with Intel® tools."

References

• Verilator
• GTKWave
• GNU Make
• Quartus Prime Lite
• Yosys
• GNU Make
• Neovim