dts: mimxrt685s/hifi4: Instantiate devs for audio

Instantiate Flexcomm zephyrproject-rtos#1, Flexcomm zephyrproject-rtos#3, DMA zephyrproject-rtos#1 and I3C - these are
peripherals responsible for audio playback and capture on the i.MX
RT685's HiFi 4 domain. Reconfigure IRQ allocation.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>

dts/xtensa/nxp/nxp_rt685_hifi4.dtsi

@@ -77,6 +77,13 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			clkctl0: clkctl@1000 {
+				/* FIXME This chip does NOT have a syscon */
+				compatible = "nxp,lpc-syscon";
+				reg = <0x1000 0x1000>;
+				#clock-cells = <1>;
+			};
+
 			gpio: gpio@100000 {
 				reg = <0x100000 0x1000>;
 
@@ -114,7 +121,7 @@
 				interrupt-controller;
 				#interrupt-cells = <1>;
 				#address-cells = <0>;
-				interrupts = <6 0 0>, <7 0 0>;
+				interrupts = <5 0 0>, <7 0 0>;
 				num-lines = <8>;
 				num-inputs = <64>;
 			};
@@ -133,11 +140,49 @@
 				#clock-cells = <1>;
 			};
 
+			dma1: dma-controller@105000 {
+				compatible = "nxp,lpc-dma";
+				reg = <0x105000 0x1000>;
+				interrupts = <6 0 0>;
+				dma-channels = <33>;
+				status = "disabled";
+				#dma-cells = <1>;
+			};
+
+			i3c0: i3c@36000 {
+				compatible = "nxp,mcux-i3c";
+				reg = <0x36000 0x1000>;
+				#address-cells = <3>;
+				#size-cells = <0>;
+				interrupts = <8 0 0>;
+				clocks = <&clkctl1 MCUX_I3C_CLK>;
+				clk-divider = <2>;
+				clk-divider-slow = <1>;
+				clk-divider-tc = <1>;
+				status = "disabled";
+			};
+
 			flexcomm0: flexcomm@106000 {
 				compatible = "nxp,lpc-flexcomm";
 				reg = <0x106000 0x1000>;
 				clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
-				interrupts = <5 0 0>;
+				interrupts = <12 0 0>;
+				status = "disabled";
+			};
+
+			flexcomm1: flexcomm@107000 {
+				compatible = "nxp,lpc-flexcomm";
+				reg = <0x107000 0x1000>;
+				interrupts = <10 0 0>;
+				clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
+				status = "disabled";
+			};
+
+			flexcomm3: flexcomm@109000 {
+				compatible = "nxp,lpc-flexcomm";
+				reg = <0x109000 0x1000>;
+				interrupts = <11 0 0>;
+				clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
 				status = "disabled";
 			};
 
@@ -165,12 +210,12 @@
 
 					adsp_int5: int@0 {
 						reg = <0>;
-						source = <ADSP_IRQ_SRC_FLEXCOMM0>;
+						source = <ADSP_IRQ_SRC_GPIO_INT0_IRQ0>;
 					};
 
 					adsp_int6: int@1 {
 						reg = <1>;
-						source = <ADSP_IRQ_SRC_GPIO_INT0_IRQ0>;
+						source = <ADSP_IRQ_SRC_DMAC1>;
 					};
 
 					adsp_int7: int@2 {
@@ -180,27 +225,27 @@
 
 					adsp_int8: int@3 {
 						reg = <3>;
-						source = <ADSP_IRQ_SRC_MU>;
+						source = <ADSP_IRQ_SRC_RTC_I3C0>;
 					};
 
 					adsp_int9: int@4 {
 						reg = <4>;
-						source = <ADSP_IRQ_SRC_NONE>;
+						source = <ADSP_IRQ_SRC_MU>;
 					};
 
 					adsp_int10: int@5 {
 						reg = <5>;
-						source = <ADSP_IRQ_SRC_NONE>;
+						source = <ADSP_IRQ_SRC_FLEXCOMM1>;
 					};
 
 					adsp_int11: int@6 {
 						reg = <6>;
-						source = <ADSP_IRQ_SRC_NONE>;
+						source = <ADSP_IRQ_SRC_FLEXCOMM3>;
 					};
 
 					adsp_int12: int@7 {
 						reg = <7>;
-						source = <ADSP_IRQ_SRC_NONE>;
+						source = <ADSP_IRQ_SRC_FLEXCOMM0>;
 					};
 
 					adsp_int13: int@8 {
@@ -306,7 +351,7 @@
 				compatible = "nxp,mbox-imx-mu";
 				reg = <0x111000 0x1000>;
 
-				interrupts = <8 0 0>;
+				interrupts = <9 0 0>;
 				rx-channels = <4>;
 
 				status = "disabled";