Implement i16x8.relaxed_q15mulr_s

As proposed in WebAssembly/relaxed-simd#40.
WebAssembly · Apr 7, 2022 · 33e5943 · 33e5943
1 parent 40a998c
commit 33e5943
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Showing 11 changed files with 58 additions and 7 deletions.
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py
@@ -533,6 +533,7 @@
     ("f32x4.relaxed_max", "makeBinary(s, BinaryOp::RelaxedMaxVecF32x4)"),
     ("f64x2.relaxed_min", "makeBinary(s, BinaryOp::RelaxedMinVecF64x2)"),
     ("f64x2.relaxed_max", "makeBinary(s, BinaryOp::RelaxedMaxVecF64x2)"),
+    ("i16x8.relaxed_q15mulr_s",   "makeBinary(s, BinaryOp::RelaxedQ15MulrSVecI16x8)"),
 
     # reference types instructions
     ("ref.null",             "makeRefNull(s)"),

diff --git a/src/gen-s-parser.inc b/src/gen-s-parser.inc
@@ -1139,9 +1139,17 @@ switch (op[0]) {
           case 'q':
             if (strcmp(op, "i16x8.q15mulr_sat_s") == 0) { return makeBinary(s, BinaryOp::Q15MulrSatSVecI16x8); }
             goto parse_error;
-          case 'r':
-            if (strcmp(op, "i16x8.replace_lane") == 0) { return makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8); }
-            goto parse_error;
+          case 'r': {
+            switch (op[8]) {
+              case 'l':
+                if (strcmp(op, "i16x8.relaxed_q15mulr_s") == 0) { return makeBinary(s, BinaryOp::RelaxedQ15MulrSVecI16x8); }
+                goto parse_error;
+              case 'p':
+                if (strcmp(op, "i16x8.replace_lane") == 0) { return makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8); }
+                goto parse_error;
+              default: goto parse_error;
+            }
+          }
           case 's': {
             switch (op[7]) {
               case 'h': {

diff --git a/src/ir/cost.h b/src/ir/cost.h
@@ -493,6 +493,7 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
       case NarrowUVecI32x4ToVecI16x8:
       case SwizzleVec8x16:
       case RelaxedSwizzleVec8x16:
+      case RelaxedQ15MulrSVecI16x8:
         ret = 1;
         break;
       case InvalidBinary:

diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
@@ -1851,6 +1851,9 @@ struct PrintExpressionContents
       case RelaxedSwizzleVec8x16:
         o << "i8x16.relaxed_swizzle";
         break;
+      case RelaxedQ15MulrSVecI16x8:
+        o << "i16x8.relaxed_q15mulr_s";
+        break;
 
       case InvalidBinary:
         WASM_UNREACHABLE("unvalid binary operator");

diff --git a/src/wasm-binary.h b/src/wasm-binary.h
@@ -887,7 +887,7 @@ enum ASTNodes {
 
   I16x8Abs = 0x80,
   I16x8Neg = 0x81,
-  I16x8Q15mulrSatS = 0x82,
+  I16x8Q15MulrSatS = 0x82,
   I16x8AllTrue = 0x83,
   I16x8Bitmask = 0x84,
   I16x8NarrowI32x4S = 0x85,
@@ -1037,6 +1037,7 @@ enum ASTNodes {
   F32x4RelaxedMax = 0xe2,
   F64x2RelaxedMin = 0xd4,
   F64x2RelaxedMax = 0xee,
+  I16x8RelaxedQ15MulrS = 0x111,
 
   // bulk memory opcodes
 

diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
@@ -917,6 +917,7 @@ class ExpressionRunner : public OverriddenVisitor<SubType, Flow> {
       case AvgrUVecI16x8:
         return left.avgrUI16x8(right);
       case Q15MulrSatSVecI16x8:
+      case RelaxedQ15MulrSVecI16x8:
         return left.q15MulrSatSI16x8(right);
       case ExtMulLowSVecI16x8:
         return left.extMulLowSI16x8(right);

diff --git a/src/wasm.h b/src/wasm.h
@@ -472,6 +472,7 @@ enum BinaryOp {
   RelaxedMaxVecF32x4,
   RelaxedMinVecF64x2,
   RelaxedMaxVecF64x2,
+  RelaxedQ15MulrSVecI16x8,
 
   InvalidBinary
 };

diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
@@ -5397,7 +5397,7 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
       curr = allocator.alloc<Binary>();
       curr->op = AvgrUVecI16x8;
       break;
-    case BinaryConsts::I16x8Q15mulrSatS:
+    case BinaryConsts::I16x8Q15MulrSatS:
       curr = allocator.alloc<Binary>();
       curr->op = Q15MulrSatSVecI16x8;
       break;
@@ -5597,6 +5597,10 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
       curr = allocator.alloc<Binary>();
       curr->op = RelaxedMaxVecF64x2;
       break;
+    case BinaryConsts::I16x8RelaxedQ15MulrS:
+      curr = allocator.alloc<Binary>();
+      curr->op = RelaxedQ15MulrSVecI16x8;
+      break;
     default:
       return false;
   }

diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
@@ -1666,7 +1666,7 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
       break;
     case Q15MulrSatSVecI16x8:
       o << int8_t(BinaryConsts::SIMDPrefix)
-        << U32LEB(BinaryConsts::I16x8Q15mulrSatS);
+        << U32LEB(BinaryConsts::I16x8Q15MulrSatS);
       break;
     case ExtMulLowSVecI16x8:
       o << int8_t(BinaryConsts::SIMDPrefix)
@@ -1842,6 +1842,10 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
       o << int8_t(BinaryConsts::SIMDPrefix)
         << U32LEB(BinaryConsts::F64x2RelaxedMax);
       break;
+    case RelaxedQ15MulrSVecI16x8:
+      o << int8_t(BinaryConsts::SIMDPrefix)
+        << U32LEB(BinaryConsts::I16x8RelaxedQ15MulrS);
+      break;
 
     case InvalidBinary:
       WASM_UNREACHABLE("invalid binary op");

diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp
@@ -1634,7 +1634,8 @@ void FunctionValidator::visitBinary(Binary* curr) {
     case NarrowSVecI32x4ToVecI16x8:
     case NarrowUVecI32x4ToVecI16x8:
     case SwizzleVec8x16:
-    case RelaxedSwizzleVec8x16: {
+    case RelaxedSwizzleVec8x16:
+    case RelaxedQ15MulrSVecI16x8: {
       shouldBeEqualOrFirstIsUnreachable(
         curr->left->type, Type(Type::v128), curr, "v128 op");
       shouldBeEqualOrFirstIsUnreachable(

diff --git a/test/lit/relaxed-simd.wast b/test/lit/relaxed-simd.wast
@@ -350,6 +350,25 @@
   )
  )
 
+ ;; CHECK-BINARY:      (func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
+ ;; CHECK-BINARY-NEXT:  (i16x8.relaxed_q15mulr_s
+ ;; CHECK-BINARY-NEXT:   (local.get $0)
+ ;; CHECK-BINARY-NEXT:   (local.get $1)
+ ;; CHECK-BINARY-NEXT:  )
+ ;; CHECK-BINARY-NEXT: )
+ ;; CHECK-TEXT:      (func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
+ ;; CHECK-TEXT-NEXT:  (i16x8.relaxed_q15mulr_s
+ ;; CHECK-TEXT-NEXT:   (local.get $0)
+ ;; CHECK-TEXT-NEXT:   (local.get $1)
+ ;; CHECK-TEXT-NEXT:  )
+ ;; CHECK-TEXT-NEXT: )
+ (func $i16x8.relaxed_q15mulr_s (param $0 v128) (param $1 v128) (result v128)
+  (i16x8.relaxed_q15mulr_s
+   (local.get $0)
+   (local.get $1)
+  )
+ )
+
 )
 ;; CHECK-NODEBUG:      (type $v128_v128_v128_=>_v128 (func (param v128 v128 v128) (result v128)))
 
@@ -481,3 +500,10 @@
 ;; CHECK-NODEBUG-NEXT:   (local.get $1)
 ;; CHECK-NODEBUG-NEXT:  )
 ;; CHECK-NODEBUG-NEXT: )
+
+;; CHECK-NODEBUG:      (func $17 (param $0 v128) (param $1 v128) (result v128)
+;; CHECK-NODEBUG-NEXT:  (i16x8.relaxed_q15mulr_s
+;; CHECK-NODEBUG-NEXT:   (local.get $0)
+;; CHECK-NODEBUG-NEXT:   (local.get $1)
+;; CHECK-NODEBUG-NEXT:  )
+;; CHECK-NODEBUG-NEXT: )