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Fix kexec kernel panic in mvpp2 (sonic-net#377)
Signed-off-by: Pavan Naregundi <pnaregundi@marvell.com>
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patch/0012-net-mvpp2-clear-BM-pool-before-initialization.patch
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,72 @@ | ||
From 09ca6f153d5d36f2f553f22dfca4e216654084fd Mon Sep 17 00:00:00 2001 | ||
From: Jenishkumar Maheshbhai Patel <jpatel2@marvell.com> | ||
Date: Thu, 18 Jan 2024 19:59:14 -0800 | ||
Subject: net: mvpp2: clear BM pool before initialization | ||
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||
Register value persist after booting the kernel using | ||
kexec which results in kernel panic. Thus clear the | ||
BM pool registers before initialisation to fix the issue. | ||
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Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") | ||
Signed-off-by: Jenishkumar Maheshbhai Patel <jpatel2@marvell.com> | ||
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> | ||
Link: https://lore.kernel.org/r/20240119035914.2595665-1-jpatel2@marvell.com | ||
Signed-off-by: Jakub Kicinski <kuba@kernel.org> | ||
--- | ||
.../net/ethernet/marvell/mvpp2/mvpp2_main.c | 27 ++++++++++++++++++- | ||
1 file changed, 26 insertions(+), 1 deletion(-) | ||
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diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | ||
index b399bdb1c..5d6309ca7 100644 | ||
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | ||
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | ||
@@ -614,12 +614,38 @@ static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) | ||
mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); | ||
} | ||
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+/* Cleanup pool before actual initialization in the OS */ | ||
+static void mvpp2_bm_pool_cleanup(struct mvpp2 *priv, int pool_id) | ||
+{ | ||
+ unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); | ||
+ u32 val; | ||
+ int i; | ||
+ | ||
+ /* Drain the BM from all possible residues left by firmware */ | ||
+ for (i = 0; i < MVPP2_BM_POOL_SIZE_MAX; i++) | ||
+ mvpp2_thread_read(priv, thread, MVPP2_BM_PHY_ALLOC_REG(pool_id)); | ||
+ | ||
+ put_cpu(); | ||
+ | ||
+ /* Stop the BM pool */ | ||
+ val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(pool_id)); | ||
+ val |= MVPP2_BM_STOP_MASK; | ||
+ mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(pool_id), val); | ||
+} | ||
+ | ||
static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) | ||
{ | ||
enum dma_data_direction dma_dir = DMA_FROM_DEVICE; | ||
int i, err, poolnum = MVPP2_BM_POOLS_NUM; | ||
struct mvpp2_port *port; | ||
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+ if (priv->percpu_pools) | ||
+ poolnum = mvpp2_get_nrxqs(priv) * 2; | ||
+ | ||
+ /* Clean up the pool state in case it contains stale state */ | ||
+ for (i = 0; i < poolnum; i++) | ||
+ mvpp2_bm_pool_cleanup(priv, i); | ||
+ | ||
if (priv->percpu_pools) { | ||
for (i = 0; i < priv->port_count; i++) { | ||
port = priv->port_list[i]; | ||
@@ -629,7 +655,6 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) | ||
} | ||
} | ||
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- poolnum = mvpp2_get_nrxqs(priv) * 2; | ||
for (i = 0; i < poolnum; i++) { | ||
/* the pool in use */ | ||
int pn = i / (poolnum / 2); | ||
-- | ||
2.25.1 | ||
|
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