Merge pull request #34 from majin2020/fmv

Fmv: fix incorrect operands and encoding for th.fmv.hw.x and th.fmv.x.hw

xtheadfmv.adoc

@@ -15,7 +15,7 @@ The table below gives an overview of the instructions:
 [cols="^3,^3,12,18",stripes=even,options="header"]
 |===
 | RV32 | RV64 | Mnemonic              | Instruction
-| Y    | N    | th.fmv.hw.x  _rd_, _fs1_ | <<#xtheadfmv-insns-fmv_hw_x>>
+| Y    | N    | th.fmv.hw.x  _fd_, _rs1_ | <<#xtheadfmv-insns-fmv_hw_x>>
 | Y    | N    | th.fmv.x.hw  _rd_, _fs1_ | <<#xtheadfmv-insns-fmv_x_hw>>
 |===
 

xtheadfmv/fmv_hw_x.adoc

@@ -5,28 +5,28 @@ Synopsis::
 Write double-precision floating-point high-bit data
 
 Mnemonic::
-th.fmv.hw.x _rd_, _fs1_
+th.fmv.hw.x _fd_, _rs1_
 
 Encoding::
 [wavedrom, , svg]
 ....
 {reg:[
     { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
-    { bits:  5, name: 'rd' },
+    { bits:  5, name: 'fd' },
     { bits:  3, name: 0x1 },
-    { bits:  5, name: 'fs1' },
+    { bits:  5, name: 'rs1' },
     { bits:  5, name: 0x0 },
-    { bits:  7, name: 0x50 },
+    { bits:  7, name: 0x60 },
 ]}
 ....
 
 Description::
-This instruction stores the contents of the specified 32-bit GP register _rd_ in the upper 32-bit of the specified double-precision FP register _fs1_.
+This instruction stores the contents of the specified 32-bit GP register _fd_ in the upper 32-bit of the specified double-precision FP register _rs1_.
 
 Operation::
 [source,sail]
 --
-fs1[63:32] := rd
+fd[63:32] := rs1
 --
 
 Permission::

xtheadfmv/fmv_x_hw.adoc

@@ -16,7 +16,7 @@ Encoding::
     { bits:  3, name: 0x1 },
     { bits:  5, name: 'fs1' },
     { bits:  5, name: 0x0 },
-    { bits:  7, name: 0x60 },
+    { bits:  7, name: 0x50 },
 ]}
 ....